Asymmetrical delay for controlling word line selection

Details Asymmetrical delay for controlling word line selection Asymmetrical delay for controlling word line selection

1988-12-21

1991-01-15

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Signals

G11C 700

Patent

active

049858653

ABSTRACT:
Asymmetrical delay circuitry comprising a chain of inverters connected to logic gates is disclosed which can be implemented at the word line driver or in the address decode circuitry of a memory.

REFERENCES:
patent: 4165540 (1979-08-01), Vinot
patent: 4656612 (1987-04-01), Allan
patent: 4803665 (1989-02-01), Kasa
patent: 4905192 (1990-02-01), Nogami et al.
"Two 13-ns 64k CMOS SRAM's with Very Low Active Power and Improved Asynchronous Circuit Techniques," by Flannagan et al., IEEE Journal of Solid-State Circuits, vol. SC-21, No. 5, Oct. 86, pp. 692-703.

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