Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
2003-01-07
2004-07-13
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
C257S692000, C257S693000, C257S697000, C257S737000, C257S738000, C257S780000
Reexamination Certificate
active
06762506
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to assembly of integrated circuit semiconductor devices onto printed circuit boards or other wiring substrates; and, in particular, to methods and apparatus useful for electrically interconnecting such devices to such substrates
BACKGROUND OF THE INVENTION
In recent years, with semiconductor packages becoming smaller and having more pins, attention has turned to a BGA (ball grid array) structure that makes use of solder balls as the external connecting terminals between the semiconductor device and a printed circuit board or other wiring substrate. For the BGA-structure semiconductor package, solder balls are installed on the inner surface (the surface opposite the principal surface where the semiconductor chip is carried) of the insulating substrate that carries the semiconductor chip. Usually, the solder balls are made of an alloy containing Sn (tin) and Pb (lead). When the semiconductor package is assembled on a wiring substrate, the solder balls are soldered onto the connecting terminals of the wiring substrate, so that electrical connection between the semiconductor chip and the wiring substrate is ensured. However, when the semiconductor chip is in operation and heat is generated, the solder balls are subjected to stress and may be damaged due to differences in thermal expansion between the semiconductor package and the wiring substrate. Damage to the solder balls leads to poor electrical connection between the elements. Consequently, measures should be taken to suppress generation of such defects. In addition, in recent years, from the viewpoint of environmental protection, there is a demand to stop using Pb.
An object of this invention is to provide methods and apparatus useful to reduce the use of Pb and lessen the potential for generation of such defects in the assembly of semiconductor devices onto wiring substrates
SUMMARY OF INVENTION
In one aspect of the invention, a semiconductor device is provided having an external connecting terminal dimensioned, configured and adapted for electrical connection to a corresponding external connecting terminal portion of a printed circuit board or other wiring substrate. The semiconductor device has a semiconductor chip with an electrode pad, an installing portion electrically connected to the electrode pad, and the external connecting terminal installed on the installing portion. The external connecting terminal comprises Sn (tin), Ag (silver), Cu (copper) and Au (gold).
In a second aspect of the invention, a wiring substrate is provided having an external connecting terminal portion dimensioned, configured and adapted for electrical connection to a corresponding external connecting terminal of a semiconductor device. The wiring substrate has an insulating substrate and a connecting terminal portion formed on the insulating substrate. The external connecting terminal portion comprises Sn, Ag, Cu and Ag.
In another aspect of the invention, a semiconductor device in accordance with the first aspect of the invention is mounted in electrical interconnection with a wiring substrate in accordance with the second aspect of the invention. Both the connecting terminal of the semiconductor device and the connecting portion of the wiring substrate comprise Sn, Ag, Cu and Ag.
In described embodiments, the installing portion of the semiconductor device has a layer comprising Au. The connecting terminal portion of the wiring substrate also has a layer comprising Au. The Au layers are formed on layers comprising Ni. The content of Au in the external connecting terminals is in the range of 0.1-12.0 wt %. It is preferred that the content of Ag in the external connecting terminals be in the range of 1.0-3.5 wt %. In addition, it is preferred that the content of Cu in the external connecting terminals be in the range of 0.5-1.0 wt %. In addition, it is preferred that an electroconductive paste containing Sn, Ag and Cu be used for assembling the semiconductor device onto the wiring substrate.
REFERENCES:
patent: 4756467 (1988-07-01), Schatzberg
patent: 5148266 (1992-09-01), Khandros et al.
patent: 5719070 (1998-02-01), Cook et al.
patent: 5937320 (1999-08-01), Andricacos et al.
patent: 6013572 (2000-01-01), Hur et al.
patent: 6310403 (2001-10-01), Zhang et al.
patent: 6486411 (2002-11-01), Miura et al.
patent: 2002/0149113 (2002-10-01), Ray et al.
patent: 2003/0030133 (2003-02-01), Terui et al.
Amagai Masazumi
Watanabe Masako
Brady W. James
Huynh Andy
Nelms David
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
LandOfFree
Assembly of semiconductor device and wiring substrate does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Assembly of semiconductor device and wiring substrate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Assembly of semiconductor device and wiring substrate will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3241922