Artificially tilted via connection

Details Artificially tilted via connection Artificially tilted via connection

2011-01-04

2011-01-04

Stark, Jarrett J (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S640000, C438S672000, C257S774000

Reexamination Certificate

active

07863185

ABSTRACT:
A semiconductor integrated circuit with tilted via connection and related method are provided, the circuit including a via layer having at least one tilted via, and a wireway layer having at least one elongated wireway disposed above the via layer, wherein the wireway connects to and partially overlaps the tilted via; and the method including forming a via layer, patterning a via trench in the via layer, forming a wireway layer, patterning an elongated wireway in the wireway layer, etching the patterned wireway and the patterned via, and filling the etched wireway and the etched via with a conductive material, wherein the filled wireway partially overlaps the filled via.

REFERENCES:
patent: 6326306 (2001-12-01), Lin
patent: 6569604 (2003-05-01), Bhatt et al.
patent: 7157366 (2007-01-01), Kim et al.
patent: 7220665 (2007-05-01), Farrar
patent: 2002/0086475 (2002-07-01), Havemann

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