Arrangement with self-amplifying dynamic MOS transistor storage

Details Arrangement with self-amplifying dynamic MOS transistor storage Arrangement with self-amplifying dynamic MOS transistor storage

1992-12-29

1994-07-05

LaRoche, Eugene R.

Static information storage and retrieval

Systems using particular element

Ferroelectric

365185, 257301, 257302, 257304, 257300, G11C 706, G11C 700

Patent

active

053273745

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

The invention relates to an arrangement with self-amplifying dynamic MOS transistor storage cells as claimed in the preamble of patent claim 1.
An arrangement of self-amplifying dynamic MOS transistor storage cells of this kind is disclosed in the publication with the title .THETA.New Dynamic RAM Cell for VLSI Memories" by T. Tsuchiya and M. Itsumi in IEEE Electron. Device Letters, Vol. EDL-3, No. 1, January 1982 (pages 7 to 10). This is a storage cell with two write lines and one read line which is composed of a MOS-FET, a MOS capacitor and a junction FET.


SUMMARY OF THE INVENTION

The invention is based on the object of disclosing an arrangement with self-amplifying dynamic MOS transistor storage cells of the type mentioned at the beginning which is of simple design, permits short access times, has a low degree of sensitivity to impacts by alpha particles and, above all, whose cell geometry can be scaled without the amount of charge which can be read out onto the bit line being substantially reduced. The object is achieved by a multiplicity of MOS transistor storage cells which are in an electrically-conductive manner connected to only one bit line in each case, which in each case have one selection transistor whose gate terminal is in an electrically conductive manner connected to a word line. Each have one storage transistor at whose gate terminal a capacitor acts in order to store information in the form of electrical charge and each MOS transistor storage cell is in an electrically conductive manner connected only to a single word line. Both the selection transistor and the storage transistor are composed in each case of a MOS transistor wherein a second terminal of the selection transistor is in an electrically conductive manner connected in each case to the bit line. The third terminal of the selection transistor and a second terminal of a storage transistor form a common drain-source node. The third terminal of the storage transistor is in an electrically conductive manner connected to a supply voltage, and one voltage-dependent resistor connects the common drain-source node tot he gate terminal of the storage transistor and a capacitor, which acts at the terminal, in such a way that the low resistance value occurs during charging and a high resistance value occurs during charging of the capacitor.
The advantage which can be achieved with the invention resides in particular in the fact that in the arrangement constructed according to the invention with self-amplifying dynamic MOS transistor storage cells, a better charge storage behavior is possible than in the storage cell cited at the beginning by virtue of higher capacitance values with the same space requirement and lower leakage current losses. Further advantages are that the MOS transistor is easy to manufacture in comparison with the junction FET and has a lower soft-error rate due to the lower degree of sensitivity to alpha beams by virtue of a smaller sensitive surface in comparison with the cell surface.
The arrangement with self-amplifying dynamic MOS transistor storage cells having voltage-dependent resistors which are formed by the gate electrode of the storage transistor and the common drain-storage region of the two transistors being composed of semiconductor materials of the same conductance type. The gate electrode of the storage transistor has a higher doping concentration than the drain-source region.
In addition, the storage transistor and the common drain-source region of the two transistors may be composed of semiconductor materials of the same conductance type with the gate electrode of the storage transistor having, however, a higher doping concentration than the common drain-source region, and wherein a metallic layer forms together with the gate electrode of the storage transistor a Schottky diode which has a lower resistance during the charging of the capacitor which acts at the gate of the storage transistor than during the discharging of this capacitor.
In another embodiment, the gate ele

REFERENCES:
patent: 4835741 (1989-05-01), Baglee
patent: 4964080 (1990-10-01), Tzeng
patent: 4990979 (1991-02-01), Otto

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