Arrangement of conductive pads on grid array package and on...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds

Reexamination Certificate

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Details

C257S738000, C257S693000, C257S697000, C257SE23015, C257SE23069

Reexamination Certificate

active

07372169

ABSTRACT:
The present invention discloses a dense arrangement in the conductors of a package and the corresponding conductive pads of a circuit board. The conductors and the corresponding conductive pads are separated into at least a first group in a peripheral region of the grid array package, and a second group in another region of the grid array package. Most in the first group of conductive pads are apart at a first pitch, most in the second group of conductive pads are apart at a second pitch which is less than the first pitch. According to the shrinking in the conductive trace on a conductive layer and the shrinking in the through hole, the first pitch and the second pitch are optimized for the maximum conductors and the corresponding conductive pads.

REFERENCES:
patent: 5729894 (1998-03-01), Rostoker et al.
patent: 2002/0070438 (2002-06-01), Ference et al.

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