Arrangement for DRAM cell using shallow trench isolation

Details Arrangement for DRAM cell using shallow trench isolation Arrangement for DRAM cell using shallow trench isolation

2000-01-19

2001-01-23

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S304000, C257S305000, C257S311000

Reexamination Certificate

active

06177697

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to semiconductor devices and their manufacture and, more particularly, to such devices and processes using a shallow trench isolation region to realize a relatively small-size capacitor. This invention relates to and may be used in conjunction with the teachings of U.S. patent application Ser. No. 09/018,711, now Patent No. 6,072,713, entitled “Data Storage Circuit Using Shared Bit Line and Method Therefor,” and of U.S. patent application Ser. No. 09/018,712, now Patent No. 6,021,064, entitled “Layout for Data Storage Circuit Using Shared Bit Line and Method Therefor,” both filed on Feb. 4, 1998, and both assigned to the instant assignee and incorporated herein by reference.
BACKGROUND OF THE INVENTION
The electronics industry continues to strive for powerful, highly functional circuits. Significant achievements in this regard have been realized through the fabrication of very large-scale integrated circuits on small areas of silicon wafers. Integrated circuits of this type are manufactured through a series of steps carried out in a particular order. The main objective in manufacturing such devices is to obtain a device which conforms to geographical features of a particular design for the device. To obtain this objective, steps in the manufacturing process are closely controlled to ensure that rigid requirements, for example, of exacting tolerances, quality materials, and clean environment, are realized.
Dynamic random access memories (DRAMs) are a widely used memory type. They are oftentimes preferred over other memory types because they can be implemented to provide an extraordinary number of memory cells in a relatively small area. The vast majority of DRAMs are implemented using MOS (metal oxide semiconductor) technology, which refers to any integrated circuitry in which n-channel and/or p-channel field effect transistors are used.
MOS devices are fabricated from various materials, including electrically conductive, electrically nonconductive and electrically semi-conductive materials. A frequently-used semi-conductive material is silicon. Silicon can be made conductive by doping (i.e., introducing an impurity into the silicon crystal structure) with either an element such as boron or with an element such as phosphorus or arsenic. In the case of boron doping, electron holes become the charge carriers and doped silicon is referred to as positive or p-type silicon. In the case of phosphorus or arsenic doping, the additional electrons become the charge carriers and the doped silicon is referred to as negative or n-type silicon.
Silicon is used either in single-crystal or polycrystalline form. Polycrystalline silicon is referred to herein as “polysilicon” or as “poly.” Due to its effectiveness as a conductor, polysilicon has been used in place of metal for many types of MOS applications. However, the higher connectivity characteristic of metal has motivated a number of semiconductor manufacturers to use a layer of refractory silicide on transistor gates to increase the device's speed.
Device speed, sometimes referred to as access time, has drawn significant attention in recent years. Particular attention has been given to increasing device speed while using ever-decreasing package sizes. For many DRAM applications, these efforts have been directed to using fewer elements to implement each memory cell in the DRAM array. For example, by using fewer transistors to implement each memory cell, the overall semiconductor real estate used per cell area can be decreased. A successful example of using one transistor to implement each memory cell is disclosed in the above-referenced U.S. patent application, entitled “Data Storage Circuit Using Shared Bit Line and Method Therefor.”
Even with a reduced number of elements used to implement such memory cells, there continues to be a need to reduce the layout area as well as the integration area required for each cell. For example, memory cells of this type typically include a capacitor or other device designed to hold a charge representing a data bit. The size of the memory cell is partly dependent on the size of this charge-holding device. To sufficiently maintain the charge over an extended period of time and over a variety of environmental conditions, the charge-holding device is typically designed to be one of the larger elements in the memory cell. Such large devices have been the subject of these efforts to reduce the layout and integration used in designing such cells.
SUMMARY
According to various aspects of the present invention, embodiments thereof are exemplified in the form of methods and arrangements for fabricating a semiconductor structure using a shallow trench isolation region to realize a relatively small capacitor. One specific implementation is directed to a process of fabricating a memory cell, comprising: selectively removing portions of a substrate using a patterned mask to form a capacitor trench and an isolation trench at least partially around the capacitor trench; forming an oxide in the isolation trench and the capacitor trench; selectively removing the oxide in the capacitor trench; doping portions of the substrate defining the base and sidewalls of the capacitor trench; forming a capacitor dielectric in the capacitor trench, leaving a portion of the trench unfilled; and forming a polysilicon layer in the unfilled portion of the capacitor trench and over the capacitor dielectric to form a plate of the storage capacitor.
Another aspect of the present invention is directed to a dynamic random access memory (DRAM) cell, comprising: a substrate; a capacitor trench disposed in the substrate; an isolation trench disposed in the substrate, at least partially around the capacitor trench; a doped region disposed in portions of the substrate defining the base and sidewalls of the capacitor trench, the doped region forming a first plate of a storage capacitor; a capacitor dielectric disposed in part of the trench; and a polysilicon layer disposed in the trench over the capacitor dielectric, the polysilicon layer forming a second plate of the first storage capacitor and having sidewalls facing the trench sidewalls to increase the capacitance per unit area of the storage capacitor.
In another embodiment, a process of fabricating a dynamic random access memory cell having an access transistor and a storage capacitor, comprises: forming, over a substrate, a patterned nitride layer exposing portions of the substrate defining an isolation region and a capacitor region within the isolation region; etching exposed portions of the substrate using the patterned nitride layer to form an isolation trench in the isolation region and a capacitor trench in the capacitor region within the isolation region; oxidizing the substrate to form a thermal oxide layer in the isolation trench and the capacitor trench; depositing an oxide layer over the thermal oxide layer to fill unfilled portions of the isolation trench and the capacitor trench; removing the patterned nitride mask; planarizing the treated surface and then forming, over the substrate, a patterned photoresist layer selectively exposing the deposited oxide layer in the capacitor trench; selectively etching the deposited oxide layer and the thermal oxide layer in the capacitor trench using the patterned photoresist as a mask; doping portions of the substrate defining the base and sidewalls of the capacitor trench using the patterned mask, the doped region forming a first plate of the storage capacitor; removing the patterned photoresist; oxidizing the substrate to grow a capacitor oxide in the capacitor trench and a gate oxide over a region of the substrate near the capacitor trench; forming a polysilicon layer over the substrate; selectively removing portions of the polysilicon layer to form a second plate of the storage capacitor over the capacitor trench and a gate electrode of the access transistor over the gate oxide; and selectively doping regions of the substrate adjacent the gate electrode to form source/drain regions of the a

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