Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2007-01-30
2007-01-30
Eckert, George (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S173000, C361S056000
Reexamination Certificate
active
10651128
ABSTRACT:
An arrangement (200) and method for scalable ESD protection of a semiconductor structure (140), a protection structure (120) providing a discharge transistor (110) path from an input/output node (130) to ground or another node if a threshold voltage is reached, wherein the discharge transistor is a self-triggered transistor having collector/drain (220) and emitter/source (210) regions, and a base/bulk region (260) having one or more floating regions (240) between the collector/drain (220) and emitter/source (210) regions. The floating region (N or P) modulates the threshold voltage Vtl for ESD protection. Vtl can be adjusted by shifting the floating region location. Splitting of the electric field into two parts reduces the maximum of the electric field. Vt1can be adjusted volt-by-volt to suit application needs. ESD capability is increased by better current distribution in the silicon. This provides the advantages of reduced die size, faster time-to-market, less redesign cost, and better ESD performance.
REFERENCES:
patent: 5982600 (1999-11-01), Cheng
patent: 2001/0007521 (2001-07-01), Chen
patent: 2001/0033003 (2001-10-01), Sawahata
patent: 1 162 664 (2001-12-01), None
patent: 1162664 (2001-12-01), None
Delage et al., “The Mirrored Lateral SCR (MILSCR) as an ESD Protection Structure: Design and Optimization Using 2-D Device Simulation,”IEEE Journal of Solid-State Circuits, Sep. 1999, vol. 34, No. 4, pp. 1283-1289.
Miller et al., “Engineering the Cascoded NMOS Output Buffer for Maximum V11”,EOS/ESD Symposium Proceedings 2000, Anaheim, CA, USA, Sep. 26-28, 2000. pp. 308-317.
Besse Patrice
Nolhier Nicolas
Zecri Michel
Balconi-Lamica Michael J.
Eckert George
Freescale Semiconductor Inc.
Ingham John
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