Area array type semiconductor package and fabrication method

Details Area array type semiconductor package and fabrication method Area array type semiconductor package and fabrication method

1998-11-30

2001-11-13

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Flip chip

C257S666000, C257S676000

Reexamination Certificate

active

06316837

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a chip package, and more particularly, to a chip package having a lead frame serving as a heat sink. The invention also relates to a method of forming the chip package.
2. Background of the Related Art
A ball grid array (BGA) semiconductor package is widely used since the package is capable of having a large number of pins in a predetermined area. Also, the external terminals of the device are short, which helps to prevent them from being bent. Such a semiconductor package may be quickly mounted on a mother board through a reflow process, thereby reducing a manufacturing time.
As shown in
FIG. 1
, a background art BGA semiconductor package includes a printed circuit board (PCB)
1
having a plurality of metal patterns (not illustrated) formed therethrough. A semiconductor chip
2
having a plurality of bonding pads (not illustrated) is adhered on the PCB
1
by an adhesive
1
a
. Metal wires
3
electrically connect each bonding pad with a corresponding metal pattern in the PCB, and a molding epoxy
4
molds a predetermined area on the PCB
1
including the semiconductor chip
2
and the metal wire
3
. A plurality of solder balls
5
, which serve as external terminals, are adhered on the lower surface of the PCB
1
. The metal patterns provide an electric path through the PCB to electrically connect the wires
3
on the upper side to the solder balls
5
on the lower side of the PCB
1
.
FIG. 2
is a flow chart illustrating steps of a fabrication method for a background art BGA semiconductor package. As shown therein, the process includes: a sawing process for dividing a plurality of semiconductor devices which are formed in a wafer into individual semiconductor chips. Next, a die bonding process is performed to attach individual semiconductor chips on a PCB. A wire bonding process is performed for connecting a plurality of bonding pads of each semiconductor chip to a plurality of metal patterns of the PCB with a plurality of wires. Next, a molding process is performed to mold a predetermined area formed on the PCB, including the semiconductor chip and the wires with a molding epoxy. Finally, a ball bonding process is performed to bond solder balls on a lower surface of the PCB to serve as external output terminals.
Since the solder balls of the above-described BGA semiconductor package are located opposite to an active surface of the semiconductor chip (i.e., the upper surface of the semiconductor chip having bond pads), there is a limitation on the minimum size of the semiconductor package due to the height necessary to allow the wires to bend from the top of the chip down to the PCB.
Also, heat generated in the semiconductor chip is not effectively radiated outside the package. Accordingly, such a package is not suitable for a high-powered semiconductor device.
SUMMARY OF THE INVENTION
It is an object of the present invention to solve the problems and disadvantages of the related art.
It is another object of the present invention to more efficiently radiate heat.
It is a further object of the invention to enable a lead frame to serve as a heat sink.
A further object of the present invention is to provide a packaging for a high-powered semiconductor device which radiates high temperature heat.
To achieve the above objects, a fabrication method for an area array type semiconductor package embodying the invention, includes the steps of forming solder bumps on bonding pads of a semiconductor chip, bonding said semiconductor chip to a lead frame; packaging a predetermined area of the lead frame and the semiconductor chip with a molding resin; and trimming and forming said lead frame.
The lead frame may include a plurality of die paddles which are attached to a corresponding plurality of semiconductor chips by a thermal conductive adhesive. A plurality of leads are attached to each of the die paddles at a certain interval and serve to radiate heat to an exterior of the package.
In a chip package embodying the invention, a chip is attached to a lead frame having a plurality of leads. A plurality of conductive media are formed on bond pads of the chip. A molding resin packages portions of the chip and the lead frame.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.


REFERENCES:
patent: 5241133 (1993-08-01), Mullen, III et al.
patent: 5355283 (1994-10-01), Marrs et al.
patent: 5834831 (1998-11-01), Kuboto et al.
patent: 5965936 (1999-10-01), Stave

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