Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2006-09-19
2006-09-19
Huynh, Andy (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S301000
Reexamination Certificate
active
07109544
ABSTRACT:
In a substrate vertical transistor cells are formed and are arranged, in a transistor cell array, row by row in an x direction and column by column in a y direction. Lower source/drain regions of the transistor cells are connected to a common connection plate. Upper source/drain regions of the transistor cells impart a contact connection for instance to a storage capacitor of a DRAM memory cell. Active trenches running between the transistor cells with word lines are formed along the x direction. The word lines form gate electrodes in sections. A potential at the gate electrode controls a conductive channel in an active region arranged in each case between the upper and the lower source/drain connection region. According to the invention, the active regions of adjacent transistor cells are sections of a contiguous layer body and are connected to one another. An accumulation of charge carriers in the active region and floating body effects are avoided without increasing the area requirement of a transistor cell.
REFERENCES:
patent: 4250519 (1981-02-01), Mogi et al.
patent: 4630088 (1986-12-01), Ogura et al.
patent: 4663644 (1987-05-01), Shimizu
patent: 4862240 (1989-08-01), Watanabe et al.
patent: 5502320 (1996-03-01), Yamada
patent: 5736761 (1998-04-01), Risch et al.
patent: 6033957 (2000-03-01), Burns, Jr. et al.
patent: 6044009 (2000-03-01), Goebel et al.
patent: 6255684 (2001-07-01), Roesner et al.
patent: 6352684 (2002-03-01), Purewal et al.
patent: 6355520 (2002-03-01), Park et al.
patent: 6492221 (2002-12-01), Hofmann et al.
patent: 2001/0032991 (2001-10-01), Hofmann
patent: 2002/0109178 (2002-08-01), Forbes et al.
patent: 195 19 159 (1996-11-01), None
patent: 198 45 004 (2000-04-01), None
patent: 101 28 928 (2002-01-01), None
patent: 101 25 967 (2002-07-01), None
patent: 61140170 (1986-06-01), None
Goebel Bernd
Manger Dirk
Schloesser Till
Huynh Andy
Slater & Matsil L.L.P.
LandOfFree
Architecture for vertical transistor cells and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Architecture for vertical transistor cells and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Architecture for vertical transistor cells and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3538829