Static information storage and retrieval – Read/write circuit – Erase
Patent
1990-10-29
1993-03-30
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Erase
365182, G11C 1300
Patent
active
051990016
ABSTRACT:
An electrically programmable memory array including a plurality of memory cells for storing data aligned in rows and columns, a plurality of word lines each connected to the gate terminals of the memory cells in a particular row, a plurality of bit lines each connected to the drain terminals of the memory cells aligned in a particular column, and a plurality of source conductors each electrically connected only to the source terminals of the memory cells in a particular row. This architecture lends itself to a finer granularity of small blocks without extra memory cell area.
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Ohya et al., "Single 5V Eprom with Sub-Micron Memory Transistor and On-Chip High Voltage Generator", NEC Corporation, Sagamihara, Kanagawa 229, Japan, pp. 570-573.
Endoh et al., "New Design Technology for Eeprom Memory Cells with 10 Million Write/Erase Cycling Endurance", ULSI Research Center, Toshiba Corporation, pp. 599-602.
Fears Terrell W.
Intel Corporation
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