Architecture for a high-performance network/bus multiplexer inte

Details Architecture for a high-performance network/bus multiplexer inte Architecture for a high-performance network/bus multiplexer inte

1998-05-21

2000-05-16

Ray, Gopal C.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710105, 710 51, 709238, 709250, 370402, G06F 1300, G06F 900, H04B 1012, H04L 1200

Patent

active

060650877

ABSTRACT:
A high-performance network/bus multiplexer that exchanges data transfer commands and data between different communications mediums, such as the Fibre Channel and one or more SCSI buses. High-performance is achieved by avoiding transmitting read bus operations through bus bridges, and by limiting contention for buses by connecting Fibre Channel host adapters to a first internal bus and SCSI adapters to a second internal bus.

REFERENCES:
patent: 5664124 (1997-09-01), Katz et al.
patent: 5671355 (1997-09-01), Collins
patent: 5751975 (1998-05-01), Gillespie et al.
patent: 5771360 (1998-06-01), Gulick
patent: 5805816 (1998-09-01), Picazo, Jr. et al.
patent: 5896513 (1999-04-01), Fisch et al.

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