Architecture and method for output clock generation on a...

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C713S401000, C326S093000

Reexamination Certificate

active

07089439

ABSTRACT:
An output clock for a memory device having a read latency more than one clock cycle includes a clock generator at a central location on the device. A clock channel couples the clock generator to output structures. A timing path emulates the address/data paths in the memory, and is responsive to an address emulation signal produced by the clock generator to provide dummy data near the output structures. An output clock signal with an adjustable phase and a dummy data reference clock signal on the input of the clock channel are generated. A phase detector near the output structures, determines whether the output clock is early, late or on time with respect to the dummy data. Logic signals are produced at the phase detector, and returned to the clock generator for adjusting the relative phase of the output clock signal.

REFERENCES:
patent: 5298866 (1994-03-01), Kaplinsky
patent: 5424980 (1995-06-01), Vinal
patent: 5432747 (1995-07-01), Fuller et al.
patent: 5561692 (1996-10-01), Maitland et al.
patent: 5587961 (1996-12-01), Wright et al.
patent: 5596539 (1997-01-01), Passow et al.
patent: 5703815 (1997-12-01), Kuhara et al.
patent: 5805872 (1998-09-01), Bannon
patent: 5818772 (1998-10-01), Kuge
patent: 5831924 (1998-11-01), Nitta et al.
patent: 5999482 (1999-12-01), Kornachuk et al.
patent: 6081462 (2000-06-01), Lee
patent: 6084805 (2000-07-01), Pawlowski
patent: 6154417 (2000-11-01), Kim
patent: 6160754 (2000-12-01), Suh
patent: 6205086 (2001-03-01), Hanzawa et al.
patent: 6212117 (2001-04-01), Shin et al.
patent: 6229161 (2001-05-01), Nemati et al.
patent: 6232797 (2001-05-01), Choi et al.
patent: 6278637 (2001-08-01), Kawaguchi
patent: 6318707 (2001-11-01), Hara et al.
patent: 6337830 (2002-01-01), Faue
patent: 6337832 (2002-01-01), Ooishi et al.
patent: 6392957 (2002-05-01), Shubat et al.
patent: 6430075 (2002-08-01), Morgan et al.
patent: 6452411 (2002-09-01), Miller et al.
patent: 6459652 (2002-10-01), Lee et al.
patent: 6462359 (2002-10-01), Nemati et al.
patent: 6490206 (2002-12-01), Kwon et al.
patent: 2001/0043482 (2001-11-01), Takeyama et al.
patent: 2002/0190265 (2002-12-01), Hsu et al.
patent: 2003/0002355 (2003-01-01), Janzen et al.
patent: WO 02/082453 (2002-10-01), None
patent: WO 02/082504 (2002-10-01), None
Nemati, Farid et al., “A Novel High Density, Low Voltage SRAM Cell with a Vertical NDR Device,” T-Ram White Paper, VLSI (1998) 2 pages, http://www.t-ram.com/technology/about/vlsi98.pdf.
Nemati, Farid et al., “A Novel Thyristor-Based SRAM Cell (T-RAM) for High-Speed, Low-Voltage, Giga-scale Memories,” T-Ram White Paper, IEDM (1999), 4 pages http://www.t-ram.com/technology/about/iedm99.pdf.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Architecture and method for output clock generation on a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Architecture and method for output clock generation on a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Architecture and method for output clock generation on a... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3657953

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.