Architecture and method for controlling a cache memory

Details Architecture and method for controlling a cache memory Architecture and method for controlling a cache memory

1996-05-20

1999-07-06

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711141, 711143, 711144, 711145, 395290, 395306, 395308, 395309, 395835, 395838, 395872, G06F 1314, G06F 1338

Patent

active

059208910

ABSTRACT:
A cache memory system comprising a first bus for connecting to a bus master and a second bus for connecting to a system memory. The system memory comprises a plurality of cacheable memory locations. A bus bridge provides an interface between the first bus and the second bus. A cache memory controller for caching data stored in the cacheable memory locations is connected to the system memory. The cache memory controller includes a snoop control circuit directly coupled to the first bus for snooping bus transactions upon the first bus and further coupled to the second bus for snooping bus transactions on said second bus.

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