4. Electrical computers and digital processing systems: processing
  5. Processing control
  6. Specialized instruction processing in support of testing,...

Michael Wisor

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Allocatable post and prefetch buffers for bus bridges

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Patent

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Architecture and method for controlling a cache memory

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Mechanism to determine actual code execution flow in a computer

Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate

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Method for utilizing virtual hardware descriptions to allow...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Method for verifying branch trace history buffer information

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate

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Profile ID: LFUS-PAI-P-376202

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