Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Metastable state prevention
Reexamination Certificate
2001-09-21
2004-08-24
Le, Don (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Metastable state prevention
C327S019000, C327S199000
Reexamination Certificate
active
06781418
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for arbiter circuits generally and, more particularly, to an arbiter with a metastable failure rate improved by delayed balance point adjustment.
BACKGROUND OF THE INVENTION
Arbitration circuitry (i.e., an arbiter) can be implemented to choose the signal that will be given control of a bus (or other resource) when two or more signals are in contention for control of the bus (i.e., identical memory requests within the same memory cycle).
Referring to
FIG. 1
, a block diagram of a circuit
10
illustrating a conventional arbiter is shown. The circuit
10
includes a NAND gate
12
cross-coupled to a NAND gate
14
(i.e., the output of the gate
12
is coupled to an input to the gate
14
and an output of the gate
14
is coupled to an input to the gate
12
). A second input of the gate
12
receives a request signal REQX and a second input of the gate
14
receives a request signal REQY. The signals REQX and REQY can be in contention. The gate
12
generates a grant signal GRANTX_B which is presented by the arbiter
10
when the signal REQX is chosen (i.e., given priority by the arbiter
10
). The gate
14
generates a grant signal GRANTY_B which is presented by the arbiter
10
when the signal REQY is chosen.
However, arbitration using the cross-coupled NAND arbiter circuit
10
can cause excessive delays due to metastable events (i.e., when the signals GRANTX_B and GRANTY_B are between a digital HIGH (“on” or 1) or a LOW (“off” or 0) state). The circuit
10
is subject to metastability when the inputs REQX and REQY change states simultaneously. Furthermore, resolution time of cross-coupled arbiters such as the circuit
10
is not predictable.
Referring to
FIG. 2
, a timing diagram
20
illustrating a resolution time aperture window of the circuit
10
is shown. The X axis represents the phase difference between REQX and REQY. The Y axis represents the resolution time of the arbiter
10
. When the signals REQX and REQY transition from LOW to HIGH simultaneously there is a resolution time Tr at which the signals GRANTX_B and GRANTY_B can be metastable. The metastable state of duration Tr or greater occurs between a REQX/REQY phase difference
22
and a REQX/REQY phase difference
24
(i.e., an aperture, in some cases 3 ps). When the phase of the signals REQX and REQY lie between the phase differences
22
and
24
the signals GRANTX_B and GRANTY_B are erroneous. The failure rate of the circuit
10
depends on the width of the metastable aperture window. The resolution time Tr is a critical failure time.
Referring to
FIG. 3
, a timing diagram
30
of the circuit
10
is shown. The signals GRANTX_B and GRANTY_B are shown crossing between a time
32
and a time
34
. The period between the time
32
and the time
34
illustrates the metastable event. The level VM is the balance point between stable and metastable operation for the circuit
10
(i.e., the signals GRANTX_B and GRANTY_B).
Referring to
FIG. 4
, a block diagram of a circuit
40
illustrating a discriminator arbiter is shown. The circuit
40
includes inverter
42
and
52
, delay circuits
44
and
46
, a NOR gate
48
, a latch/discriminator circuit
50
, and a NAND gate
54
. The delay circuit
44
provides a delay for the settling time of the circuit
40
. The delay
46
provides a delay to match the circuit
40
propagation times for the signals REQX and REQY. The circuit
40
is in a metastable state when the signals GRANTX_B and GRANTY_B balance. The circuit
40
operates similarly to the circuit
10
.
Referring to
FIG. 5
, a detailed block diagram of the circuit
50
of
FIG. 4
is shown. The circuit
50
can be a jamb latch circuit. The circuit
50
includes a discriminator circuit
60
, a latch circuit
62
, a device
64
, a device
66
, a device
68
and a device
70
. The devices
64
and
66
are inverting amplifiers (i.e., inverters). The device
64
has an input coupled to the output of the device
66
and an output coupled to the input of the device
66
. When the circuit
50
is implemented using circuit
60
and without the circuit
62
, the circuit
50
may act as an asynchronous jamb latch. When the circuit
50
is implemented using the circuit
62
and without the circuit
60
, the circuit
50
may act as a synchronous jamb latch. When the signals A and B balance, the circuit
50
can be metastable.
Pulse discrimination using the jamb latch
50
as a pulse discriminator with an arbiter circuit
40
can cause excessive delays due to metastable events similarly to the circuit
10
(i.e., when the circuit
50
is metastable). Resolution time of the discriminator arbiter circuit
40
is not predictable. The failure rate of the discriminator arbiter circuit
40
can depend on the width of the metastable aperture window similarly to the circuit
10
.
It would be desirable to have an arbiter and/or discriminator that has a narrow metastable aperture, has a high MTBF, and reduces the effects of metastable conditions.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a first circuit and a second circuit. The first circuit may be configured to arbitrate a plurality of input request signals and present one or more first control signals. The second circuit may be configured to control the arbitration in response to an adjustable balance point of the input request signals, where the balance point is adjusted to reduce the duration of a metastable state of the first circuit.
The objects, features and advantages of the present invention include providing an arbiter with an improved metastable failure rate by delayed balance point adjustment that may (i) reduce an arbiter aperture, (ii) increase mean time between failures, (iii) reduce arbiter delays associated with metastable events, (iv) be used in multi-port memories, (v) effect arbitration between two (or more) asynchronous requests, (vi) reduce the probability of arbiter errors, (vii) reduce the effects of metastable conditions, (viii) have delayed contention, (ix) have one or more adjustable delays, and/or (x) control resolution time.
REFERENCES:
patent: 4398105 (1983-08-01), Keller
patent: 4403192 (1983-09-01), Williman
patent: 4924220 (1990-05-01), Mihara et al.
patent: 4998030 (1991-03-01), Cates
patent: 6188249 (2001-02-01), Becker
patent: 6498513 (2002-12-01), Reynolds
patent: 6674306 (2004-01-01), Reynolds
patent: 6690203 (2004-02-01), Nystrom et al.
Grahame K. Reynolds, “Metastability Recovery Circuit”, U.S. Ser. No. 09/877,657, Filed Jun. 7, 2001.
Grahame K. Reynolds, “Method and Apparatus for the Use of Discriminators for Priority Arbitration”, U.S. Ser. No. 09/877,659, Filed Jun. 7, 2001.
Grahame K. Reynolds, “Multiport Arbitration Using Phased Locking Arbiters”, U.S. Ser. No. 09/877,660, Filed Jun. 7, 2001.
Grahame K. Reynolds, “Discriminator Circuit”, U.S. Ser. No. 09/877,658, Filed Jun. 7, 2001.
Cypress Semiconductor Corp.
Le Don
Maiorana P.C. Christopher P.
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