Approach to optimizing an ILD argon sputter process

Details Approach to optimizing an ILD argon sputter process Approach to optimizing an ILD argon sputter process

1997-12-31

2003-11-11

VerSteeg, Steven H. (Department: 1753)

Chemistry: electrical and wave energy

Processes and products

Coating, forming or etching by sputtering

Reexamination Certificate

active

06645353

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the field of integrated circuit manufacturing and more particularly to etch processes in the manufacture of integrated circuits.
2. Description of Related Art
In the fabrication of semiconductor-based integrated circuit devices or chips, numerous conductive regions and layers are formed in or on a semiconductor substrate. To isolate underlying regions or layers, an interlayer dielectric (ILD) is formed over those regions. In most modern ILD processes, chemical vapor deposition (CVD) is used to deposit the ILD. In a CVD process, a solid film of, for example, oxide is formed on a substrate by the reaction of an oxide source gas and the substrate. The gas mixture, temperature, RF power, pressure, and gas flow rate, among other factors, may be varied in the CVD process to achieve the desired characteristics of the ILD.
In general, the ILD has to conform to exacting specifications. One standard provides that there should be no voids between metal (signal) lines at any layer that is above the metal surface and void height, or greater than 25% of the metal spacing and void width. Another standard also provides that composite ILD stress at the post-polished thickness should be between 1.0×10
8
to 9.0×10
8
dyne/cm
2
, compressive. If the ILD is not compressive enough, it is subject to cracking and short circuits. If the ILD is too compressive, it may provide poor oxide metal adhesion that can lead to open circuits within the device.
There are a number of methods of depositing an ILD. One method is shown in
FIGS. 1-5
. In
FIG. 1
, substrate
10
represents a semiconductor substrate and any device layers or structures underlying conductive, e.g., metal, structures
11
thereon. Metal structures
11
include, for example, tungsten (W), aluminum (Al), aluminum-copper (Al—Cu) alloy, or aluminum-copper-silicon (Al—Cu—Si) alloy. In order to isolate metal structures
11
from subsequent layers, a first dielectric layer
30
is deposited using, for example, a plasma-enhanced CVD method. In one example, tetraethylorthosilicate (TEOS) is used as the oxide source in the deposition.
FIG. 2
shows the conformal deposition of first dielectric layer
30
over substrate
10
and metal structures
11
.
Once dielectric layer
30
is deposited,
FIG. 3
shows the subsequent processing step wherein the deposition profile of first dielectric layer
30
is tapered by a sputter etch
40
, such as for example, an argon sputter etch. As a general proposition, argon sputter etching removes approximately four times more material from 45° angles than from horizontal surfaces. Therefore, corners are reduced to a much greater extent than level surfaces. A portion of removed dielectric layer
30
from the upper edges, is redeposited in areas between metal structures
11
. The redeposited dielectric material is represented by reference numeral
45
in FIG.
3
. Redeposited dielectric
45
helps to taper the deposition profile of first dielectric layer
30
.
FIG. 4
shows the further processing step wherein second dielectric layer
50
of, for example, oxide is conformally deposited over the structure, also using, for example, a plasma-enhanced CVD method with TEOS as the oxide source. Second dielectric layer
50
is generally thicker than first dielectric layer
30
. In one example, first dielectric layer
30
is deposited to a thickness of approximately 2,000-5,800 Å while second dielectric layer is deposited to a thickness of approximately 15,000-30,000 Å Second dielectric layer
50
is then planarized as illustrated in
FIG. 5
by, for example, a chemical-mechanical polish such as a silicon dioxide (SiO
2
) slurry in potassium hydroxide (KOH) and water.
Directing attention to the sputter etch described above, prior art sputter etchers of ILD are typically performed at high pressure and zero gauss. Using a high pressure and zero gauss sputter etch results in a reduction of the mean free path which increases the redeposition rate of the dielectric material. This improves the gapfill between metal lines
11
and the amount of dielectric that is redeposited
45
. Additionally, the elimination of magnetic fields (i.e., zero gauss) reduces the possibility of gate oxide “charging.” Gate oxide charging occurs when the sputter etch proceeds too far and exposes a portion of metal line
11
to plasma energy. The plasma energy into the exposed metal damages the gate oxide of, for example, a transistor to which the metal line
11
is attached.
FIG. 6
shows a conventional etch system for conducting a sputter etch. Etch system
70
includes etch chamber
75
attached to seat
80
. Inside etch chamber
75
is a pedestal
85
that supports a wafer for processing. An argon plasma is introduced into etch chamber
75
through a gas distribution plate
97
. The argon plasma bombards the top surface of wafer
90
as part of the etch process. A commonly used etcher is for example the AMAT5000™ manufactured by Applied Materials. The AMAT5000™ includes magnets
95
, on its outer surface, over etch chamber
75
, including magnet(s)
95
adjacent the top surface and magnetic coils
95
adjacent the side of etch chamber
75
. The magnets provide a pulsed electromagnetic field to aid in various plasma etch processes.
FIG. 7
illustrates a top view of etch system
70
, such as the AMAT5000™, having an etch chamber
75
with magnets
95
displaced about and outside of etch chamber
75
. As noted above, is however, it has been determined that sputter etch processes yield better device results (i.e., gate oxide charging, etc.) when the pulsed electromagnetic field is turned off and the etch is performed in a zero gauss state. In one prior art ILD reformation process embodiment, a sputter etch is performed at a pressure in the range of 100 mTorr with a magnetic field reduced to at, or near, zero, from a standard value of 50-60 gauss.
FIG. 8
illustrates a schematic top section view of wafer
90
that would undergo a sputter etch process as part of the fabrication process. Wafer
90
is divided into a plurality of individual devices.
FIG. 8
shows wafer
90
and represents two individual devices, device
55
and device
60
.
FIG. 9
graphically shows the typical etch rate of an argon sputter etch on a prior art semiconductor wafer. As illustrated in
FIG. 9
, the etch rate of an argon sputter etch varies across the wafer diameter. The duration of the sputter etch is typically calculated by determining a mean etch rate based on an etch rate profile such as presented in FIG.
9
.
FIG. 9
shows that for a 100 millimeter (mm) diameter wafer, the etch rate of an argon sputter etch process is much slower at the center of the wafer, such as for example at device
55
, than at the outer portions of the wafer, such as for example at device
60
. In practice, however, where device
55
and device
60
are similarly fabricated devices, it is desirable that device
55
and device
60
see the same or a similar etch rate. Unfortunately, current etch systems, such as the AMAT5000™ operated at high pressure and zero gauss, cannot provide the desired etch rate uniformity.
Etch rate uniformity is particularly important in ILD processing. In ILD processing, the sputter etch controls voids formed between metal lines by displacing first dielectric material in the areas between the metal lines and, if present, controlling voids to be small and to be below the metal surface. With an etch rate profile illustrated in
FIG. 9
having a low performance etch rate represented by Y
1
(which is, for example, over device
55
), the etch may not be sufficient to temper any voids or ensure that the voids are below the top surface of the metal lines. Such inefficient sputter etching and the presence of voids can lead to shorts. If, on the other hand, the etch rate performance is too great, such as for example as may be the case on the outer portions of wafer
90
and represented in
FIG. 9
by Y
2
(which is, for example, the location of device
60
), the etch can hit the t

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