Etching a substrate: processes – Gas phase etching of substrate – Application of energy to the gaseous etchant or to the...
Reexamination Certificate
2002-06-10
2004-11-16
Ahmed, Shamim (Department: 1765)
Etching a substrate: processes
Gas phase etching of substrate
Application of energy to the gaseous etchant or to the...
C216S017000, C216S041000, C438S700000, C438S706000, C438S717000, C438S725000
Reexamination Certificate
active
06818141
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuits and methods of manufacturing integrated circuits. More particularly, the present invention relates to definition of the subresolution trench features between polysilicon wordlines using the CVD deposited bilayer ARC as a hard mask.
BACKGROUND OF THE INVENTION
Semiconductor devices or integrated circuits (Ics) can include millions of devices, such as, transistors. Ultra-large scale integrated (ULSI) circuits can include complementary metal oxide semiconductor (CMOS) field effect transistors (FET). Despite the ability of conventional systems and processes to fabricate millions of devices on an IC, there is still a need to decrease the size of IC device features, and, thus, increase the number of devices on an IC.
One limitation to the smallness of IC critical dimensions is conventional lithography. In general, projection lithography refers to processes for pattern transfer between various media. According to conventional projection lithography, a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film or coating, the photoresist. An exposing source of radiation illuminates selected areas of the surface through an intervening master template, the mask, for a particular pattern. The radiation can be light, such as ultra-violet light, vacuum ultra-violet (VUV) light and deep ultraviolet light. The radiation can also be x-ray radiation, e-beam radiation, etc.
The lithographic photoresist coating is generally a radiation-sensitive coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive image of the subject pattern.
Exposure of the lithographic coating through a photomask or reticle causes the image area to become selectively either more or less soluble (depending on the negative or positive photoresist coating) in a particular developer. The more soluble areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer.
The photoresist material or layer associated with conventional lithographic technologies is often utilized to selectively form various IC structures, regions, and layers. Generally, the patterned photoresist material can be utilized to define structures associated with an integrated circuit (IC). A conventional lithographic system is generally utilized to pattern photoresist material to form gate stacks or structures. As the features in semiconductor patterning become smaller and smaller, the photoresist thickness needs to be reduced in order to sustain reasonable aspect ratio. A thinner resist may not be suitable for etch application due to premature resist erosion. This limitation provides a need for the use of hard mask processes.
According to one conventional process, a high temperature oxide (HTO) hard mask is provided above polysilicon/oxide layers to pattern the small trenches between gate stacks. The hard mask must be thin enough so that it can be etched without eroding the patterned photoresist above it. The hard mask must also be thick enough to withstand an etch process that can completely remove uncovered portions of the polysilicon layer. Accordingly, the hard mask must have a precise thickness to appropriately pattern the gate stacks. The removal of the hard mask material after the gate stack is defined is also problematic due to the potential for damage to the exposed underlying material.
An anti-reflective coating (ARC) has been conventionally provided underneath the photoresist material or on top of the hard mask to reduce reflectivity and thereby, reduce resist notching and lifting and variation of critical dimension of the obtained pattern. Generally, the ARC (organic or inorganic) layer is a relatively thin layer which cannot be used as a hard mask because of the limited thickness flexibility due to optical design constrains.
Thus, there is a need to pattern IC devices using non-conventional techniques. Further, there is a need for a process of forming a small subnominal trench in the gate stack that does not require a conventional hard mask step. Yet further, there is a need for a hard mask layer that can function as an anti-reflective coating with enough thickness flexibility to be used as a masking material for trench definition and can be removed from the defined polygate structures without any damage to underlying materials. Even further still, there is a need for a gate mask process that effectively balances optical and etching efficiencies.
Conventionally, a carbon bilayer ARC, such as SiON or SiRN having a thickness of 100 to 600 Angstroms can be used over a high temperature oxide (HTO) hardmask to act as anti-reflective material needed for control of the critical dimensions during lithographic exposures. The ARC materials allow controlled patterning of an underlining HTO hardmask using conventional deep ultraviolet (DUV) photolithographic and dry etch techniques. The DUV photoresist is applied, exposed and developed on top of the ARC layer forming a narrow trench structures in the resist film.
Dry etching the ARC and the underlying HTO hardmask layer transfers narrow space features to the HTO hard mask. After the hardmask is patterned, the remaining resist and the ARC material must be removed to allow the formation of the spacer material which allows further reduction of the narrow space between two structures formed during HTO etch. In conventional processes, the stripping of carbon bilayer ARC by dry etching or conventional wet stripping techniques damages the sensitive underlying, oxide-nitride-oxide (ONO) stack and degrades the quality of the device. The combined HTO and spacer hardmask is used to etch the exposed polysilicon with the intention to form submicron spaces between adjacent poly lines in the core.
Thus, there is a need for a carbon
itride CVD-bilayer ARC that acts as an anti-reflective coating, hard mask and can be easily stripped without damage to the underlying layer. Further, there is a need to consume the thin resist during the, top nitride etch, and consume the nitride and the some of the carbon layers during HTO hard mask etch such that the remaining carbon ARC can be stripped by plasma ashing, which does not damage the ONO stack. Further, there is a need to use bilayer CVD ARC as it is superior to more conventional organic spin-on ARC because bilayer CVD ARC is conformal, providing a uniform reflectivity everywhere. Even further, there is a need for simultaneous printing of peripheral poly circuitry.
SUMMARY OF THE INVENTION
An exemplary embodiment is related to a method of providing a carbon
itride CVD bilayer ARC that acts as an anti-reflective coating hard mask and can be easily stripped without damage to the underlying layer. This method can include providing a first layer (e.g., carbon) and a second layer (e.g., nitride) as a CVD bilayer ARC above a desired substrate and patterning spaces in the first layer using a DUV resist and patterning the second carbon layer of the ARC using the first layer as a mask. This method also includes patterning HTO hardmask layer using patterned bilayer ARC as a mask. The remaining carbon ARC layer is ashed away after complete patterning of narrow spaces in the HTO hardmask layer.
Another exemplary embodiment is related to a method of using low energy ashing to reduce damage effects on an oxide-nitride-oxide stack. This method can include providing a photoresist layer above a bilayer anti-reflective coating (ARC) above a hardmask layer above a polysilicon layer above an oxide-nitride-oxide stack above a substrate, patterning trenches in the photoresist layer, patterning the bilayer ARC and the hardmask layer using the patterned photoresist layer and the bilayer ARC as a mask, plasma ashing to remove the remaining bilayer ARC layer, providing spacer material over the patterned hardmask layer, removing portions of the spacer material, and defining spaces in the polysilicon layer using the
Ghandehari Kouros
Plat Marina V.
Advanced Micro Devices , Inc.
Ahmed Shamim
LandOfFree
Application of the CVD bilayer ARC as a hard mask for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Application of the CVD bilayer ARC as a hard mask for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Application of the CVD bilayer ARC as a hard mask for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3353699