Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-11-07
2006-11-07
Lindsay, Jr., Walter (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S232000, C438S231000
Reexamination Certificate
active
07132340
ABSTRACT:
Methods (600, 700) are disclosed for minimizing the effect of pocket shadowing in the fabrication of an angled pocket implant (32) extending underlying a gate region (21) of a transistor (10), particularly in SRAM devices (400). The pocket shadowing is minimized by initially forming a relatively thick resist layer (810) overlying the semiconductor device (800), then the resist layer thickness (810y) is reduced (trimmed) to a reduced thickness (860y) by using a subsequent post-development dry or wet resist-reduction etch process (630, 730). The etch process (630, 730) also increases corner rounding (860r), thereby reducing pocket shadowing of the angled implant from nearby features or the resist (228, 328, 860). The pocket shadow reduction may be accomplished by first forming (610, 710) the relatively thick resist layer (810) overlying the semiconductor device (400, 800). The resist layer (860) is then wet and/or dry etched (630, 730) to trim the resist thickness (860y) and to round the corners (860r) of the resist (442, 860). In combination, these changes reduce shadowing of angled implants from nearby structures and resist edges. The method may further comprise a first implant (720) (e.g., an LDD implant) before the resist etch trim (730), and a second angled pocket implant (740) after the etch trim (730) to permit individually optimizing the resist thickness and CD for each implant. Thus, only one lithography step is required, while cross diffusion of the LDD implant is mitigated. Transistors (443and446, 448, or830and840) formed in this manner may yield improved performance when incorporated into SRAM (400, 800) since the probability that such transistors will be more closely matched is increased.
REFERENCES:
patent: 6569606 (2003-05-01), Wu et al.
patent: 6642148 (2003-11-01), Ghandchari et al.
patent: 6762459 (2004-07-01), Choi et al.
patent: 2003/0203550 (2003-10-01), Lai et al.
patent: 2005/0167397 (2005-08-01), Chen et al.
Houston Theodore W.
Sadra Kayvan
Lindsay, Jr. Walter
McLarty Peter K.
LandOfFree
Application of post-pattern resist trim for reducing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Application of post-pattern resist trim for reducing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Application of post-pattern resist trim for reducing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3679216