Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-08-30
2010-02-16
Menz, Laura M (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S200000, C438S423000
Reexamination Certificate
active
07662688
ABSTRACT:
The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.
REFERENCES:
patent: 5156990 (1992-10-01), Mitchell
patent: 6265292 (2001-07-01), Parat et al.
patent: 6486517 (2002-11-01), Park
patent: 6599804 (2003-07-01), Buluccea et al.
patent: 6624022 (2003-09-01), Hurley et al.
patent: 6627937 (2003-09-01), Shinkawata
patent: 6649968 (2003-11-01), Wolstenholme
patent: 6656783 (2003-12-01), Park
patent: 6674145 (2004-01-01), Hurley et al.
patent: 6690051 (2004-02-01), Hurley et al.
patent: 6713346 (2004-03-01), Wolstenholme
patent: 6914287 (2005-07-01), Tran
patent: 6949445 (2005-09-01), Rhodes et al.
patent: 7045410 (2006-05-01), Mehrad et al.
patent: 7141468 (2006-11-01), Sadra et al.
patent: 7193277 (2007-03-01), Sadra et al.
patent: 7208390 (2007-04-01), Singh et al.
patent: 7314800 (2008-01-01), Sadra et al.
patent: 7445965 (2008-11-01), Akagawa et al.
patent: 7452750 (2008-11-01), Lo et al.
patent: 2005/0087810 (2005-04-01), Sadra et al.
patent: 2005/0124102 (2005-06-01), Wang et al.
patent: 2005/0145949 (2005-07-01), Sadra et al.
patent: 2005/0266628 (2005-12-01), Wang et al.
patent: 2006/0084230 (2006-04-01), Sadra et al.
patent: 2007/0080387 (2007-04-01), Liu et al.
patent: 2008/0003772 (2008-01-01), Sadra et al.
patent: 2008/0145985 (2008-06-01), Chi
Chatterjee Amitava
Sadra Kayvan
Sridhar Seetharaman
Tsao Alwin
Brady III Wade J.
Keagy Rose Alyssa
Menz Laura M
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
LandOfFree
Application of different isolation schemes for logic and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Application of different isolation schemes for logic and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Application of different isolation schemes for logic and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4181772