Application of different isolation schemes for logic and...

Details Application of different isolation schemes for logic and... Application of different isolation schemes for logic and...

2006-11-28

2006-11-28

Schillinger, Laura M. (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S201000, C438S224000

Reexamination Certificate

active

07141468

ABSTRACT:
The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.

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