Apparatus suitable for providing synchronized clock signals...

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay

Reexamination Certificate

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Details

C713S400000, C713S500000, C713S503000, C257S208000, C327S161000

Reexamination Certificate

active

06857081

ABSTRACT:
A device for transmitting clock signals to a microprocessor is disclosed. The device is configured to receive a clock signal and distribute the signal synchronically to multiple output sites on the device. The synchronized clock signals are transmitted from the various device sites to multiple sites on the microprocessor.

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“Clock skew reduction in ASIC logic design: a methodology for clock tree management” Balboni, A.; Costi, C.; Pellencin, M.; Quadrini, A.; Sciuto, D.; CAD of Integrated CKts and Systems, IEEE Trans on, vol.: 17, Issue: 4, Apr. 1998, pp.:344-356.

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