Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
2000-03-31
2003-03-25
Heckler, Thomas M. (Department: 2185)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Reexamination Certificate
active
06539489
ABSTRACT:
FIELD OF THE INVENTION
The present invention is directed to an apparatus, method and system for having at least one slave system of a master-slave asynchronous communication system synchronize certain slave events or operations to master clocking signals in a master system by monitoring the phase of the master clocking signals and by regulating the slave event or clocking signals.
BACKGROUND INFORMATION
In a master-slave asynchronous communication system, which may include a master station or system (or other “source” device) and one or more slave stations or systems (or other “destination” devices), a slave system (or systems) may be used to synchronize the timing of its slave events with respect to some master clocking event or signal of the master system. In this regard, certain slave systems may use counters or programmable counter arrangements to synchronize their slave events with respect to master clocking events or signals by counting the time between the master clocking events or signals. In the master station or system, the master system has some master clocking signal having a clocking frequency or period. The master clocking signal may be used to provide a timing reference for data events or operations. The master system may use synchronization pulses to provide a timing reference for the slave system.
In particular, certain events or operations of the slave system may be synchronized to certain master clocking signals of the master system by using counter arrangements to count the time between the synchronizing pulses or other master clocking signals that correspond to the master clock cycle. In such systems, however, if the time between the master clocking events or signals increases (for example, to a time that may be on the order of about hundreds of milliseconds or even seconds), then the master clock rate may need to be decreased if the number of counters or other logic arrangements in the slave system are limited. In this regard, for example, if erasable programmable logic devices (“EPLDs”) (which use “floating-gate” MOSFET technology), application specific integrated circuits (“ASICs”) or other comparable devices are used, any limitations in their available logic resources (such as the number of available flip-flops) may limit the number of logic devices (such as flip-flops) that may be used to provide a sufficiently accurate counter system in the slave system. This may correspondingly limit the measurement accuracy, and may also limit the time interval or window that may be accurately measured by the phase monitoring logic in the slave system of the master-slave asynchronous communication system.
Thus, a system designer may need to compromise the design of a particular application of a master-slave asynchronous system based on the resolution requirement (which depends on the maximum phase error between the master clocking event and the corresponding slave clocking event) if there are limited logic resources (such as the number of flip-flops). It is believed, however, that such a compromise may result in reduced phase measurement accuracy when the slave system determines the phase of the master slave events to synchronize the clocking events of the slave system.
SUMMARY OF THE INVENTION
One aspect of an exemplary embodiment of a method of the present invention is directed to providing a method for synchronizing a slave system and a master system, the method including the steps of providing a slave clock signal based on a communicated master clock signal, providing a time frame in the slave system, wherein the time frame is defined by a minimum time and a maximum time, and a phase of the slave clock signal corresponds to an actual time, determining if the slave clock signal is in the time frame, and regulating the slave clock signal, if it is not in the time frame, so that the slave clock signal occurs within the time frame.
Another aspect of an exemplary embodiment of a method of the present invention is directed to providing a method for synchronizing a slave system and a master system, the method including the steps of providing a master clock signal in the master system, communicating the master clock signal to the slave system so as to provide a communicated master clock signal, providing a time frame in the slave system, wherein the time frame is defined by a minimum time and a maximum time, providing a slave clock signal based on the communicated master clock signal, wherein a phase of the slave clock signal corresponds to an actual time, determining if the slave clock signal is in the time frame, determining if the actual time is no greater than the minimum time, if the slave clock signal is not in the time frame, and regulating the slave clock signal, if it is not in the time frame, by phase shifting the slave clock signal so that it occurs after the minimum time and before the maximum time in the time frame.
Still another aspect of an exemplary embodiment of the present invention is directed to providing a system for synchronizing a slave system and a master system, the synchronizing system including a first generator that generates a time frame, wherein the time frame is defined by a minimum time and a maximum time, a second generator that generates a slave clock signal based on a communicated master clock signal, wherein a phase of the slave clock signal corresponds to an actual time, a processor that determines if the slave clock signal is in the time frame, and a regulator that regulates the slave clock signal, if it is not in the time frame, so that the slave clock signal occurs within the time frame.
Yet another aspect of an exemplary embodiment of the present invention is directed to providing a system for synchronizing a slave system and a master system, the synchronizing system including means for providing a slave clock signal based on a communicated master clock signal, wherein a phase of the slave clock signal corresponds to an actual time, means for providing a time frame, wherein the time frame is defined by a minimum time and a maximum time, means for determining if the slave clock signal is in the time frame, and means for regulating the slave clock signal, if it is not in the time frame, so that the slave clock signal occurs within the time frame.
Still another aspect of an exemplary embodiment of the present invention is directed to providing a system for synchronizing a slave system and a master system, the system including a first generator that generates a master clock signal in the master system, a communication apparatus that is adapted to communicate the master clock signal to the slave system so as to provide a communicated master clock signal, a second generator that generates a time frame in the slave system, wherein the time frame is defined by a minimum time and a maximum time, a third generator that generates a slave clock signal based on the communicated master clock signal, wherein a phase of the slave clock signal corresponds to an actual time, a processor that determines if the slave clock signal is in the time frame, and that determines if the actual time is no greater than the minimum time if the slave clock signal is not in the time frame, and a regulator that regulates the slave clock signal, if it is not in the time frame, by phase shifting the slave clock signal so that it occurs after the minimum time and before the maximum time in the time frame.
Yet another aspect of an exemplary embodiment of the present invention is directed to providing a system for synchronizing a slave system and a master system, the system including means for providing a master clock signal in the master system, means for communicating the master clock signal to the slave system so as to provide a communicated master clock signal, means for providing a time frame in the slave system, wherein the time frame is defined by a minimum time and a maximum time, means for providing a slave clock signal based on the communicated master clock signal, wherein a phase of the slave clock signal corresponds to an actual time, means for determinin
Heckler Thomas M.
Siemens Aktiengesellshaft
Staas & Halsey , LLP
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