Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-11-28
2006-11-28
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07143372
ABSTRACT:
An apparatus and a method for measuring the efficiency of a system-on-a-chip (SoC). The SoC efficiency measuring apparatus includes a storage to store information about each of intellectual properties (IP) embedded on the SoC, a receipt efficiency calculator to set an IP corresponding to information stored in the storage as a source IP and to calculate a receipt efficiency from the source IP based on the information about the source IP, a transmission efficiency calculator to set an IP corresponding to information stored in the storage as an object IP and to calculate a transmission efficiency to the object IP based on the information about the object IP, and a displayer to display the efficiencies calculated by the receipt efficiency calculator and the transmission efficiency calculator. Accordingly, the efficiency of the SoC can be measured before manufacturing.
REFERENCES:
patent: 6427224 (2002-07-01), Devins et al.
patent: 6694488 (2004-02-01), Raghunathan et al.
patent: 6725432 (2004-04-01), Chang et al.
patent: 2003/0009730 (2003-01-01), Chen et al.
Dinh Paul
Samsung Electronics Co,. Ltd.
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