Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2000-11-10
2004-08-03
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S719000
Reexamination Certificate
active
06772379
ABSTRACT:
TECHNICAL FIELD
The present invention relates to an apparatus for verifying the data retention in non-volatile memories, particularly in EPROM memories. More particularly such invention relates to an apparatus for verifying the data retention in EPROM memories in an integrated circuit.
BACKGROUND OF THE INVENTION
In the manufacturing of integrated circuits it is possible to incur in the manufacturing of non-volatile memory cells which can show defects in data storage and which can carry to the failure of a device wherein they are comprised. Also the memory cells must be tested in order to detect the defective cells which will be eliminated.
In the case wherein a non-volatile memory is used in an integrated circuit, it is necessary to have a circuitry in order to effectuate the data retention tests in each single memory cell. Such operations must consider the possibility to effectuate thermal stress simulations to which a device containing the non-volatile memory will be subjected after the assemblage on the final chip.
The circuitry which must be performed to satisfy such needs must be as little bulky as possible and it must increase as little as possible the time to effectuate such test.
A latch matrix, per se, used for block
12
is of a type well known in the art and thus the details need not be described.
SUMMARY OF THE INVENTION
According to the present invention, an apparatus for verifying the data retention in a non-volatile memory comprising at least one multiplexer and at least one shift register, is provided. The multiplexer and shift register are disposed so that the data of the non-volatile memory are input to the multiplexer. The output of the multiplexer is in turn input to the shift register. A logical circuit using suitable commands controls the transfer of data from the multiplexer to the shift register, the loading of data and the shifting of output data from the shift register.
Thanks to the present invention, it is possible to provide an apparatus for verifying the data retention in non-volatile memories which is small in size, which is fast and which provides the assurance of the reliability of the memory cells.
REFERENCES:
patent: 5146431 (1992-09-01), Eby et al.
patent: 5153853 (1992-10-01), Eby et al.
patent: 5258986 (1993-11-01), Zerbe
patent: 5325367 (1994-06-01), Dekker et al.
patent: 5331188 (1994-07-01), Acovic et al.
patent: 5553082 (1996-09-01), Connor et al.
patent: 5592493 (1997-01-01), Crouch et al.
patent: 5617531 (1997-04-01), Crouch et al.
patent: 5726930 (1998-03-01), Hasegawa et al.
patent: 5764655 (1998-06-01), Kirihata et al.
patent: 5768182 (1998-06-01), Hu et al.
patent: 6034884 (2000-03-01), Jung
patent: 6272588 (2001-08-01), Johnston et al.
patent: 6496947 (2002-12-01), Schwarz
Bellomo Ignazio
Camera Alessandro
Sandri Paolo
Carlson David V.
Jorgenson Lisa K.
SEED IP Law Group PLLC
STMicroelectronics S.r.l.
Ton David
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