Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-03-27
2009-11-24
Kerveros, James C (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S724000
Reexamination Certificate
active
07624320
ABSTRACT:
A system-on-chip (SoC) test apparatus is disclosed. The system-on-chip (SoC) testing apparatus reduces a test time due to a small amount of overhead in the case of testing an AMBA-based system-on-chip (SoC) using a TIC, an EBI, and a Test Harness, and maintains AMBA- or TIC- compatibility simultaneously while performing scan input/output operations.
REFERENCES:
patent: 6425100 (2002-07-01), Bhattacharya
patent: 7181663 (2007-02-01), Hildebrant
patent: 7237161 (2007-06-01), Volz
patent: 2005/0240850 (2005-10-01), Ohwada et al.
Kim Jin-Kyu
Min Pil-Jae
Park Sung-Ju
Song Jae-Hoon
Yi Hyun-Bean
Birch & Stewart Kolasch & Birch, LLP
Industry-University Cooperation Foundation Hanyang University
Kerveros James C
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