Apparatus for testing semiconductor memory device

Details Apparatus for testing semiconductor memory device Apparatus for testing semiconductor memory device

1998-05-14

2000-03-07

Nelms, David

Static information storage and retrieval

Read/write circuit

Testing

36518907, 365191, 365210, G11C 700

Patent

active

060349050

ABSTRACT:
A semiconductor memory testing apparatus of the present invention includes a signal generating unit for generating an input signal, an address signal and an expected value signal, a judging unit for judging a quality by comparing the output signal outputted by a semiconductor memory device under test with the expected value signal and generating a judgement signal, and a defect analyzing memory unit having a defect analyzing memory for storing the judgement signal. An address space of the address signal generated by the signal generating unit is set according to classification of the memory cells of the semiconductor memory device under test, and the signal generating unit includes an address space switching unit for switching over the address space as the necessity may arise. The defect analyzing memory unit sets a predetermined address in accordance with the address space to which the address signal belongs.

REFERENCES:
patent: 5666049 (1997-09-01), Yamada et al.
patent: 5706234 (1998-01-01), Pilch, Jr. et al.

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