Apparatus for testing a fixed logic value interconnection betwee

Details Apparatus for testing a fixed logic value interconnection betwee Apparatus for testing a fixed logic value interconnection betwee

1994-12-15

2000-09-12

Iqbal, Nadeem

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714 30, G01R 3128

Patent

active

061192562

ABSTRACT:
A device which includes a first integrated circuit and a second IC for applying a fixed logic value to an input of the first integrated circuit. A conventional implementation uses pull-up and pull-down resistors, but these resistors necessitate an additional step and additional elements for the testing of the relevant interconnections. The device is improved in that an output of the second IC, which outputs the logic value during normal operation, is controlled via test logic during testing. As a result, the interconnections between the output of the second IC and the input of the first IC are tested in the same way and as part of the testing of the other interconnections between the first and second integrated circuits.

REFERENCES:
patent: 4879717 (1989-11-01), Sauerwald et al.
patent: 4967142 (1990-10-01), Sauerwald et al.
patent: 5029166 (1991-07-01), Jarwala et al.
patent: 5384533 (1995-01-01), Tokuda et al.
patent: 5390191 (1995-02-01), Shiono et al.
patent: 5487074 (1996-01-01), Sullivan
"Boundary-Scan Test: A Practical Approach", by H. Bleeker et al, pp. 1-17.
"256 X 8-bit Static CMOS EEPROM With I.sup.2 C Bus Interface", Data Development, Oct. 1987, pp. 535-539.

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