Static information storage and retrieval – Read/write circuit – Serial read/write
Reissue Patent
1998-01-21
2001-02-20
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Serial read/write
C365S189020, C365S230020, C365S239000
Reissue Patent
active
RE037060
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to the serial programming of random access memory arrays, and particularly random access memory arrays contained within larger devices such that the number of input/output pins available for programming is limited.
Typically, in the programming of random access memory arrays, one provides the data to be stored and address information that indicates where in the array the data are to be stored. To read the array, the address of the locations desired would be provided. In addition, Output Enable and read/write control signals are typically provided. Typically, the programming data, address data, and control signals are fed in parallel to a buffer. Change of the read/write control signal to a write state then causes the programming data in the buffer to be written to the appropriate places in the array as determined by the address data.
A programming scheme such as that just described ordinarily is performed in parallel, requiring a large number of input/output (I/O) lines. For example, in the case of a 64×32-bit array, eleven (11) address lines are required—i.e., six lines for the 64-bit dimension (2
6
=64) and five lines for the 32-bit dimension (2
5
=32). In addition, the programming data are normally transferred in 8-bit bytes, necessitating another eight (8) lines, and the clock and control signals require at least two additional lines, for a total in that case of at least twenty-one (21) lines required for writing. The device is similarly read out into an output buffer, preferably under control of the same address lines as are used for input, when the read/write control signal changes to a read state. The output of the buffer is then read in parallel using, typically, eight lines. Thus, twenty-one lines are required for reading as well.
If the random access memory is a discrete memory device, the number of lines required for reading or writing is not of much concern, because the available I/O pins on the device are not required for other functions. However, random access memory arrays are frequently embedded in larger devices. For example, copending commonly-assigned U.S. patent application Ser. No. 08/442,795, filed May 17, 1995, which is hereby incorporated by reference in its entirety, describes a programmable logic device having a large number of interconnected programmable logic regions. In addition, there are a smaller number of random access memory regions embedded in the device (in that example, the random access memory is static random access memory). In that device, there is heavy competition for I/O pins, which must be shared by logic inputs and outputs, programming inputs, testing inputs and outputs, etc.
One way of reducing the number of pins required to access a large array device is to use serial techniques. For example, commonly-assigned U.S. Pat. No. 4,930,107 shows a method for serially programming an EPROM-type programmable logic device. However, where the array device is a random access memory, special considerations arise that may make serial programming more difficult.
For example, in the random access memory arrangement described above, programming, address and control data are input into a buffer, and written from the buffer into the random access memory on a change of state of the read/write control bit in the buffer. To serially program such a random access memory, one would serially load the input buffer, then flip the read/write control bit to a write state. If there is more than one array, their input buffers would be chained together and loaded in a single serial loading operation. The serially loaded data bits would be arranged so that at the end of the serial loading, the read/write control position of each buffer is in the write state, to cause writing into each array. However, the status of the read/write control bit in each buffer (except the last one) would change continually as the programming data are clocked in. Each time a bit representing the write state passed through the read/write control position of each buffer, the corresponding array would be written with unintended data. Even in the case of a single array, if the read/write control position is not the last position in the buffer, erroneous writing can occur. And even if the read/write control position is the last position, it still may not be desirable for writing to occur as soon as the intended write state bit reaches that read/write control position.
Reading of the random access memory occurs in a similar way. Specifically, address data are written into the input buffers and the read/write control bit or bits are changed to a read state, causing the data in the array that is identified by the address in the buffer to be written to output buffers which can then be read either serially or in parallel (again, to optimize pin allocations, serial reading would be preferred). Here again, as the address data are clocked in, unintended reading or writing may occur as the read/write control bit changes state.
It would be desirable to be able to provide for serial reading and writing of random access memory while preventing unintended reading and writing of the memory as data are clocked into the input buffers.
SUMMARY OF THE INVENTION
It is an object of this invention to provide for serial reading and writing of random access memory while preventing unintended reading and writing of the memory as data are clocked into the input buffers.
In accordance with the invention, there is provided serially progammable random access memory having at least one random access memory array. Each array includes a plurality of random access memory bits, a plurality of data input lines for entering data to be stored in the random access memory array, a plurality of address input lines and an address decoder for entering address information indicating in a write mode in which of the plurality of random access memory bits the data to be stored is to be stored and for indicating in a read mode which of the plurality of random access memory bits are to be output from the random access memory array, and a read/write control input. The random access memory array is in a read mode when a read/write control signal applied to the read/write control input is in a first logic state and is in a write mode when the read/write control signal applied to the read/write control input is in a second logic state. For each of the at least one random access memory array, a set of input/programming registers is connected to the data input lines, the address input lines and the read/write control input, for inputting programming data for the random access memory array, which programming data include the address information and a registered control signal to be applied to the read/write control input, as well as the data to be written when the input/programming registers are used for writing. The input/programming registers are chained together such that the data to be stored, the address information and the registered control signal can be entered serially into the registers. A read/write control circuit allows selective operation of the at least one random access memory array in one of (a) a first mode in which the random access memory array is in one of (i) a read mode, and (ii) a write mode, regardless of the registered control signal, and (b) a second mode in which the random access memory array is in one of (i) a read mode, and (ii) a write mode, under control of the registered control signal.
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Chang Wanli
Huang Joseph
Sung Chiakang
Altera Corporation
Dinh Son T.
Fish & Neave
Ingerman Jeffrey H.
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