Apparatus for scan test of SRAM for microprocessors having full

Details Apparatus for scan test of SRAM for microprocessors having full Apparatus for scan test of SRAM for microprocessors having full

1997-06-23

1999-03-09

Shah, Alpesh M.

Excavating

371 211, G06F 1100

Patent

active

058812180

ABSTRACT:
An apparatus for allowing a RAM array within an SRAM to be tested via scan ATPG is disclosed. A first clocked flip-flop has a data input latched high, a scan-in input latched high, a clock input coupled to a signal source generating a periodic waveform, a scan-enable input coupled to a scan enable signal, and an output. The first flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high. A second clocked flip-flop has a data input coupled to the output of the first flip-flop, a scan-in input latched high, a clock input coupled to the signal source, a scan enable input coupled to the scan enable signal, and an output. The second flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high. An AND gate has a first input coupled to an inversion of the scan enable signal, a second input coupled to the output of the second flip-flop, and an output coupled to a write enable input to the SRAM.

REFERENCES:
patent: 5412662 (1995-05-01), Honma et al.
patent: 5459733 (1995-10-01), Alapat
patent: 5499249 (1996-03-01), Agrawal et al.
patent: 5604756 (1997-02-01), Kawata
patent: 5696770 (1997-12-01), Lo
patent: 5761489 (1998-06-01), Broseghini et al.

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