Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1998-01-26
2000-11-21
Nelms, David
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
365 52, 365 63, G11C 700
Patent
active
061512575
ABSTRACT:
An electronic circuit die is presented including a plurality of first and second input/output (I/O) pad buffer cells. The first I/O pad buffer cells include at least a latch for latching data signals received at a pad in the cell. Adjacent ones of these first I/O pad buffer cells are conductively coupled together using conductive trace pins. The second I/O pad buffer cells include a pad that receives clocking signal which are supplied to the latches of the first I/O pad buffer cells. Accordingly, data signals received at the pads of the die are latched in the pad as opposed to the core logic of the die. One benefit of providing the latching of data signals in the pad is that conductive traces between the latches and the core logic need not be precisely matched, thus reducing cost. Also, the first I/O pad buffer cells can be similarly constructed, thus reducing the complexity and cost of manufacture for the die.
REFERENCES:
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patent: 5300835 (1994-04-01), Assar et al.
patent: 5515540 (1996-05-01), Grider et al.
patent: 5594442 (1997-01-01), Paulos et al.
patent: 5812490 (1998-09-01), Tsukude
patent: 5900021 (1999-05-01), Tiede et al.
Jeffrey Smith E.
Kelly Timothy W.
Kiss Stephen W.
Self Keith M.
Intel Corporation
Le Thong
Nelms David
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