Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2006-02-07
2006-02-07
Auve, Glenn A. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C711S113000, C711S118000, C711S119000, C711S120000, C711S121000, C345S557000
Reexamination Certificate
active
06996657
ABSTRACT:
An apparatus for providing packets in a peripheral interface circuit of an I/O node of a computer system. The apparatus includes a buffer that may be configured to accumulate data received on a first bus. The apparatus further includes a control unit coupled to the buffer which may be configured to transmit a data packet containing a first number of bytes of the data in response to detecting that any of the bytes of the data is invalid. The control unit may be further configured to transmit the data packet containing a second number of bytes of the data in response to detecting that all of the bytes are valid.
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U. S. Appl. No. 09/399,281, filed Sep. 17, 1999.
Askar Tahsin
Chambers Eric G.
Advanced Micro Devices , Inc.
Auve Glenn A.
Curran Stephen J.
Kivlin B. Noäl
Mason Donna K.
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