Electrical computers and digital data processing systems: input/ – Interrupt processing – Interrupt inhibiting or masking
Reexamination Certificate
1996-08-01
2001-02-20
Wiley, David A. (Department: 2781)
Electrical computers and digital data processing systems: input/
Interrupt processing
Interrupt inhibiting or masking
Reexamination Certificate
active
06192441
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a device for controlling interrupts generated by different entities associated with a microprocessor.
2. Discussion of the Related Art
Conventionally, a microprocessor includes a certain number of inputs for receiving interrupt signals from different entities. These signals have the function of notifying the microprocessor of the occurrence of particular events within the entities.
A conventional interrupt control processes these particular events in real time. In other words, when an event occurs in an entity, the program executed by the microprocessor is stopped at once to process this event by executing a routine associated therewith. Such real time processing is necessary to avoid a situation where an event having occurred in an entity is not taken into account by the microprocessor upon the occurrence of another event in the same entity.
A disadvantage of conventional systems is that real time interrupt control requires the provision of a very fast microprocessor, even if such speed is not needed for the processing of the programs associated with the operation of the system.
Another disadvantage is that it is possible, in a succession of interrupts, that an interrupt of a given type appears even though the processing of a preceding interrupt of the same type (using the same routine) is not finished, because it was interrupted upon occurrence of other events. The processing of this preceding interrupt will not be able to be finished, which can cause an operation error.
SUMMARY OF THE INVENTION
The present invention aims at overcoming these disadvantages by providing an interrupt control device which postpones the processing of the interrupts by the microprocessor.
The invention also aims at providing a device by means of which no event is omitted by the microprocessor.
The invention further aims at modifying the priority rank associated with each entity issuing an interrupt without it being necessary to modify the connections between the different elements of the system.
To achieve these aims, the present invention provides a device for controlling the interrupts of a microprocessor based on events occurring in at least one entity associated with the microprocessor, the device including means for organizing the storage of words representative of at least the origin and type of the interrupts issued by the entity.
According to an embodiment of the present invention, these words are stored in at least one area of a memory dedicated thereto. The organizing means includes a first register containing the address of the first word of the memory area and a logic circuit for calculating the address in the memory area at which this word is to be stored.
According to an embodiment of the present invention, the storage of the words in the memory area is performed circularly. Each word includes a bit indicative of the existence of an interrupt to be processed and set at an active state as the word is stored.
According to an embodiment of the present invention, the bit indicative of the existence of an interrupt to be processed in the word which contains it is set at an inactive state by the microprocessor when reading this word. The bit indicates the existence of an interrupt to be processed further and is used to determine the saturation of the memory area.
According to an embodiment of the present invention, the device includes at least one FIFO register which receives the words of said entity and provides them to the address calculation logic circuit.
According to an embodiment of the present invention, the device is for controlling interrupts issued by several entities, each entity being associated with a memory area and the device includes a second register containing, for each area, a code indicative of its size.
According to an embodiment of the present invention, the device is associated with an interrupt register connected to be read by the microprocessor The interrupt register has a number of bits at least equal to the number of memory areas. Each bit indicates, by its state, respectively, active or inactive, the presence or the absence of an interrupt stored in the area associated therewith. The setting of a bit at its active state is performed by the address calculation circuit and the setting of all bits to the inactive state is performed by the microprocessor, at each reading.
According to an embodiment of the present invention, the interrupt register is associated with a mask register of same size, the bits of which are set by the microprocessor. In addition, a circuit for generating a signal sent to the microprocessor, where this signal indicates the presence of an unmasked interrupt, is also included.
According to an embodiment of the present invention, the interrupt register further contains at least bits indicative of interrupts generated by the address calculation logic circuit, at least one of these bits indicating the saturation of one memory area.
According to an embodiment of the present invention, the microprocessor determines the processing priority of the interrupts contained in one memory area with respect to those contained in another memory area.
These objects, features and advantages as well as others, of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments in relation to the accompanying drawings.
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Athenes Claude
Moniot Pascal
Galanthay Theodore E.
Morris James H.
SGS-Thomson Microelectronics S.A.
Wiley David A.
Wolf Greenfield & Sacks P.C.
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