Apparatus for making test data and method thereof

Details Apparatus for making test data and method thereof Apparatus for making test data and method thereof

1997-04-24

2000-02-29

Tu, Trinh L.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

G01R 3128

Patent

active

060322802

ABSTRACT:
An apparatus for producing test data used for detection of defects which occur in manufacturing functional blocks of a processor LSI is provided with a test pattern producing part for detecting a fault of the functional block at a block edge of the functional block, based on logic data of the functional block, with regard to one operation of the processor LSI which operates the functional block for the test data to be produced, the test pattern at the block edge of the functional block being such as to satisfy the conditions of an input signal to the block edge of the functional block when an instruction on the one operation is executed, and the conditions of an output signal from the block edge of the functional block being observable from the outside of the processor LSI when the instruction is executed. The apparatus also has an instruction sequence producing part for producing an instruction sequence in a machine language for the processor LSI by which an output from the block edge of the functional block becomes detectable at an external terminal of the processor LSI.

REFERENCES:
patent: 4996659 (1991-02-01), Yamaguchi et al.
patent: 5719881 (1998-02-01), Yonetoku
patent: 5754561 (1998-05-01), Masui
Lee et al., "Hierarchical Test Generation under Intensive Global Functional constraints", 29th ACM/IEEE Design Automatic Conference, 1992, paper 17.1, pp. 261-266.
Konijnenburg et al., "Test Pattern Generation with Resistors", International Test Conference, 1993, paper 30.1, pp. 598-605.
Vishakantaitah et al., "CHEETA: Composition of Hierarchical Sequential Tests Using ATKET", International Test Conference, 1993, paper 30.2, pp. 606-615.
Lee et al., "Architectural Level Test Generation for Microprocessors", IEEE Transactions on computer-aided Design of Integrated Circuits & System, vol. 13 No. 10 Oct. 1994, pp. 1288-1300.

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