Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
Reexamination Certificate
1998-07-17
2001-01-16
De Cady, Albert (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Replacement of memory spare location, portion, or segment
C714S733000
Reexamination Certificate
active
06175936
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to computer memories, and in particular to hardware for built-in self-test for embedded memories.
BACKGROUND OF THE INVENTION
Computer memory arrays on chips involve a very large number of individual cells. For dynamic random access memories, the number of cells is very large. As a result, even small defect rates arising out of the manufacturing process result in an unacceptably low yield. Test procedures are applied to DRAM chips, usually on wafer-by-wafer basis. Every chip on each wafer is tested on specialized equipment, which identifies the locations of defective cells. Location information is then supplied to a controller for a laser repair device, which achieves a hardware fix. The repaired wafer is then tested again.
Such test and repair procedures are expensive because of the need to employ specialized test and repair equipment.
In SRAM chips, and other chips with embedded logic, repairs are not ordinarily carried out. The size of arrays in SRAM chips and other such chips has been small enough that, even without repairs, acceptable yield is obtained. Also, because SRAM chips are generally more specialized and manufactured in smaller quantities, the cost of configuring laser repair machines must be averaged over a relatively small number of wafers, when compared to DRAM chips.
In chips with embedded memories, it has become possible to have test procedures carried out by logic on the chip, known as built-in self-test units. The built-in self-test units for SRAM chips carry out a verification process resulting in a simple indication of whether there is a defect in the memory array. As defective chips are simply discarded, no additional information is required.
However, array size in SRAM chips is steadily increasing. Accuracy in manufacturing techniques is not increasing sufficiently rapidly to maintain yields. Furthermore, additional components, which were formerly in separate devices, are also being added to SRAM chips. The added components increase functionality of the chips, and are sometimes referred to as a system on a chip. These devices mean that individual chips are much more expensive, making discarding faulty chips undesirable.
SUMMARY OF THE INVENTION
There may be provided in addition to a main memory array, a spare memory array, and a reconfiguration memory device for mapping from defective cells in the main memory array to designated cells in the spare memory array. According to one aspect of the invention, an apparatus for testing computer memories disposed on a substrate is provided. The apparatus has memory test hardware for generating signals for testing a first memory array and a second memory array. The first memory array and the second memory array may be any two of the main memory array, the spare memory array, and the reconfiguration memory device, or the apparatus may be adapted for testing all three memory arrays. The memory test hardware may include a controller for generating control signals, a data generator coupled to the controller for generating data signals, and an address generator coupled to the controller for generating address signals. The test device may further include an output data evaluator and repair unit for receiving signals from the main memory array and the spare memory array and for detecting faults in those arrays. This configuration permits the testing of multiple memory arrays with a minimum of hardware.
According to another aspect of the invention, a method for testing computer memories disposed on a substrate includes the steps of generating test signals from memory test hardware disposed on the substrate to test a first memory array disposed on the substrate, and generating test signals from the memory test hardware to test a second memory array disposed on the substrate. The memory arrays may include a main memory array, a spare memory array, the memory of a reconfiguration control unit for mapping from defective cells in the main memory array to the spare memory array.
According to another aspect of the invention, a method for testing computer memories located on a substrate includes providing test signals to a first memory array and a second memory array. A single output data evaluator and repair unit receives signals from both the first and second memory arrays, and determines the existence of faults in the first and second memory arrays. The data evaluator and repair unit also determines the location of the faults to the degree of precision required.
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Higgins Frank P.
Kim Ilyoung
Cady Albert De
Duane Morris & Heckscher
Lucent Technologies - Inc.
Ton David
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