Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1998-12-09
2001-01-16
Tu, Trinh L. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S805000, C714S795000, C711S004000
Reexamination Certificate
active
06175943
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus for controlling addresses of symbol data for correcting errors of digital data, and more particularly, to an apparatus for controlling addresses of symbol data for correcting errors in a digital versatile disc (DVD) system.
2. Description of the Related Art
In a DVD system, data recorded in a disk is read during reproduction and an error correction of a Reed-Solomon (RS) product code type is performed. At this time, the read data is aligned in a virtual two dimensional state. The error corrections are respectively performed in the directions of horizontal and vertical axes. Accordingly, a two dimensional error correction effect is obtained.
FIG. 1
shows structures of a data sector
10
and of an error correcting code (ECC) block
12
for the error correction in the DVD system. The data recorded on a disk (not shown) is read by a series of one-bit data columns. A bit stream in units of 16 bits is demodulated in a symbol data pattern of eight bits in a demodulating circuit (not shown). The error corrections with respect to the symbol data are respectively performed in the horizontal and vertical directions in the virtually arranged ECC block
12
.
The ECC block
12
of the symbol data for the error correction is formed of 172 bytes×12 rows×16 data sectors excluding a parity and is comprised of pure symbol data forming 172 bytes×192 rows including the
16
frame rows of the data sector. A data structure of 182 bytes×192 rows is formed by adding an inner parity (PI) of 10 bytes for the error correction of the symbol data. The entire data of 182 bytes×208 rows to which an outer parity PO of 16 bytes is added to each of 182 columns is modulated and is recorded on a disk.
Here, when the respective symbol data are B
i,j
(i=0 through 207, j=0 through 181), a surplus polynomial R
j
(X) comprising 172 columns including outer parity is shown in the following Equation (1).
Rj
(
X
)
=
∑
i
=
192
207
B
i
,
j
·
X
207
-
i
=
{
I
j
(
X
)
·
X
16
}
mod
{
G
PO
(
X
)
}
(
1
)
wherein,
I
j
(
X
)
=
∑
j
=
0
191
B
i
,
j
·
X
143
-
i
and
G
PO
(
X
)
=
∏
k
=
0
15
(
X
+
α
k
)
Also, the surplus Polynomial R
j
(X) comprising the 208 rows including inner parity is shown in the following Equation (2).
R
i
(
X
)
=
∑
j
=
172
181
181
B
i
,
j
·
X
181
-
j
=
{
I
i
(
X
)
·
X
10
}
mod
{
G
PI
(
X
)
}
(
2
)
wherein,
I
i
(
X
)
=
∑
j
=
0
171
B
i
,
j
·
X
171
-
i
,
G
PI
(
X
)
=
∏
k
=
0
9
(
X
+
α
k
)
,
and &agr; represents a primitive root of a primitive polynomial. Here, the positions of the respective symbol data other than the values of the respective symbol data are included in the components to be error corrected. Namely, the symbol data demodulated from the bit stream read from the disk must be recorded on a virtual original position in the ECC block
12
of FIG.
1
. Accordingly, it is possible to detect and correct the data having errors during the error correction. When the symbol data demodulated from the bit stream is recorded one byte later or one byte earlier, and thus not recorded on the row to be recorded, a large number of error are generated. Accordingly, the error correction is not possible.
In the DVD system, a data unit of 91 bytes shown in the sector
10
of
FIG. 1
is defined as even and odd frames in order to process various data. The respective frames are divided by frame syncs. The structures of the frame syncs are shown in FIG.
3
A. The respective frames are earlier, thus forming the sector
10
of FIG.
1
. The ECC block
12
which is a basic unit of the error correction is comprised of the sectors. Accordingly, a proper error correction is performed.
Therefore, when the symbol data is stored for the error correction, an apparatus for controlling addresses is required by which it is possible to improve the efficiency of the error correction by storing the symbol data in the memory so that the positions of the respective symbol data precisely correspond to the alignment of the symbol data of the ECC block.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an apparatus for controlling addresses of symbol data for an error correction by which it is possible to perform the error correction in an optimal state although a slip occurs in a disk by storing demodulated symbol data in a memory, precisely corresponding to an ECC block using position information extracted from a bit stream read during the reproduction of the disk.
Accordingly, to achieve the above object, there is provided an apparatus for controlling addresses for storing symbol data obtained by demodulating a bit stream read from a disk in a memory for an error correction, comprising a sync detecting portion for receiving the bit stream and detecting a frame sync and an ID (identification) sync, a frame sync number generating portion for correcting the detected series of frame syncs and outputting information on the positions of the frame syncs, an ID error correcting portion for outputting an error corrected ID using an ID parity included in the symbol data, an ID sync number detecting portion for receiving the error corrected ID and the ID sync, sequentially comparing the ID sync with a sync frame structure, checking whether a correct ID sync is input, and outputting information on the position of the ID, an address generating portion for receiving the frame sync, the ID sync, and the information on the positions of the respective syncs, generating addresses of symbol data corresponding to a predetermined position of an ECC block, and outputting the addresses to the memory, and a controlling portion for controlling the respective detecting and generating portions.
Also, the sync detecting portion detects the received frame sync as a concerned frame sync when the received frame sync bit coincides with the frame sync by more than predetermined number of bits.
Also, the degree of a scope within which the sync detecting portion senses the sync frame is controlled by the controlling portion.
Also, the information on the positions of the frames are the numbers of the detected concerned sync frames and the numbers of the sync frames are sequentially set according to the positions corresponding to the frame syncs.
Also, the information on the position of the ID is the ID number of a concerned sector.
Also, the frame sync number generating portion compares the received frame syncs with the frame syncs to check whether the former coincides with the latter and corrects the frame syncs.
REFERENCES:
patent: 4254500 (1981-03-01), Brookhart
patent: 4707805 (1987-11-01), Narusawa et al.
patent: 6029208 (2000-02-01), Kim
patent: 57-123578 (1982-08-01), None
patent: 60-253065 (1985-12-01), None
patent: 63-160066 (1988-07-01), None
patent: 2-214070 (1990-08-01), None
patent: 3-187070 (1991-08-01), None
Samsung Electronics Co,. Ltd.
Sughrue Mion Zinn Macpeak & Seas, PLLC
Tu Trinh L.
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