Semiconductor device manufacturing: process – With measuring or testing – Electrical characteristic sensed
Reexamination Certificate
2000-08-22
2003-05-13
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
With measuring or testing
Electrical characteristic sensed
C257S678000
Reexamination Certificate
active
06562641
ABSTRACT:
TECHNICAL FIELD
The present invention relates to apparatus and methods of testing and assembling semiconductor packages, and more specifically, to testing and assembling fine ball grid array (FBGA) packages having circuit-bearing interconnect components.
BACKGROUND OF THE INVENTION
As the trend toward decreasing the size of microelectronic packages continues, challenges associated with packaging and testing it semiconductor devices are continuously encountered. Fine ball grid array (FBGA) semiconductor packages, for example, offer reduced package volumes and desirable performance characteristics. Testing of FBGA semiconductor packages, however, may be difficult, and the difficulty may increase as the size of the FBGA package decreases.
FIG. 1
is a cross-sectional elevational view of a typical FBGA package
10
. The FBGA package
10
includes a bumped die
12
having a plurality of bond pads
14
formed thereon. An electrically conductive ball or bump
16
(typically composed of solder or a gold alloy) is formed on each bond pad
14
, and is attached to associated contact pad
18
formed on a substrate
20
, such as a test carrier or a printed circuit board. A conductive trace
22
is formed on the surface of the substrate
20
and is attached to one of the contact pads
18
. The conductive traces
22
typically fan out from the bumped die
12
and may be connected to other electronic components or to test equipment. FBGA packages of the type shown in
FIG. 1
are more fully described, for example, in U.S. Pat. Nos. 5,663,106 and 5,777,379 to Karavakis et al, and in U.S. Pat. No. 5,821,608 to DiStefano et al, which patents are incorporated herein by reference.
As mentioned above, for testing of the FBGA package
10
, the substrate
20
may be a test carrier that temporarily engages the conductive bumps
14
of the bumped die
12
. Suitable test carriers for testing unpackaged die
12
are described, for example, in U.S. Pat. No. 5,519,332 to Wood et al, incorporated herein by reference. Generally, such carriers are suitable for use with automated equipment and assembling procedures utilized in high-volume semiconductor manufacturing. Design considerations of such test carriers include the carrier's ability to transmit and receive electrical signals over a wide temperature range, thermal management characteristics, power and signal distribution characteristics, cost and reusability.
Testing of the bumped die
12
generally includes four levels of testing. A first or “standard probe” level includes the standard tests for gross functionality of die circuitry. A second or “speed probe” level includes testing the speed performance of the die for the fastest speed grades. A third or “burn-in die” level involves thermal cycling tests intended to drive contaminants into the active circuitry and to detect early failures. And a fourth or “known good die (KGD)” level includes testing to provide a reliability suitable for final products.
To ensure proper transmission of the test signals and output signals, the conductive bumps
16
may be temporarily connected with the contact pads
18
of the substrate
20
by reflowing the bumps, thereby soldering the bumps to the contact pads. After the testing is complete, the conductive bumps
16
may be reflowed to disconnect the bumps from the contact pads
18
. After testing, the bumped die
12
is usually placed in operation by attaching the bumped die
12
to a printed circuit board or another semiconductor component. Again, the conductive bumps
16
are placed in contact with the contact pads
18
of the printed circuit board, and are reflowed to bond the conductive bumps
16
to the contact pads
18
, thereby attaching the bumped die
12
to the printed circuit board.
Connecting and disconnecting the conductive bumps
16
from the contact pads
18
, however, involves time-consuming processes and may damage the conductive bumps
16
or the contact pads
18
. Also, even though a bumped die
12
tests successfully using the test carrier, the final connection between the conductive bumps
16
of the bumped die
12
and the contact pads
18
of the printed circuit board may not always be good. Therefore, it is usually desirable to conduct additional testing of the bumped die
12
after it has been assembled with the printed circuit board in the final FBGA package
10
.
Currently, conductive bumps
16
may range in height h (
FIG. 1
) from 0.75 mm down to 0.15 mm depending upon the die or semiconductor component. Typical “pitch” or spacing between adjacent conductive bumps
16
may range from 0.65 mm down to 0.13 mm (130 micron) or less. Furthermore, a semiconductor die or memory chip may have several hundred conductive bumps. Due to the extremely small sizes of the conductive bumps, the spacing between bumps, and the large number of bumps in typical FBGA packages, testing of such packages presents extreme challenges. For example, when the conductive bumps
16
of the bumped die
12
are attached to the contact pads
18
of the substrate
20
, it is often not possible to measure a test signal at (or near) each of the conductive bumps
16
to determine the performance of a particular circuit or connection within the bumped die
12
. This is especially true for those conductive bumps
16
which are not along the edges of the FBGA package
10
. As the trend toward reducing the size of FBGA packages continues, the difficulties associated with testing such packages will continue to increase.
SUMMARY OF THE INVENTION
The present invention is directed to apparatus and methods of testing and assembling fine ball grid array (FBGA) packages having circuit-bearing interconnect components. In one aspect, a circuit-bearing interconnect component includes a substrate having a plurality of first conductive members disposed therethrough, a plurality of conductive traces coupled to the first conductive members and extending away from the first conductive members to a distal portion of the substrate, and a plurality of second conductive members disposed on the distal portion and coupled to the conductive traces. The substrate may be rigid or flexible. The first conducting members are located within an engagement area that is adapted to be engageable with a semiconductor component having a plurality of conductive bumps wherein each conductive bump engages one of the first conductive members. The first conductive members may include conductively-plated via or conductive pins. The circuit-bearing interconnect component may advantageously permit efficient, accurate, and reliable testing of the semiconductor component when the semiconductor component is attached to a semiconductor device, such as a printed circuit board.
In an alternate aspect, a semiconductor package includes a semiconductor component having a plurality of conductive bumps disposed thereon, a substrate including a plurality of first conductive members disposed within an engagement area, each first conductive member being attached to one of the conductive bumps and extending through a thickness of the substrate, the substrate further having at least one distal portion extending away from the engagement area, a plurality of conductive traces each having a first end electrically coupled with one of the first conductive members and a second end An extending away from the one first conductive member and onto the at least one distal portion, and a plurality of second conductive members disposed on the at least one distal portion, each second conductive member being coupled to one of the conductive traces.
REFERENCES:
patent: 5519332 (1996-05-01), Wood et al.
patent: 5629838 (1997-05-01), Knight et al.
patent: 5663106 (1997-09-01), Karavakis et al.
patent: 5734560 (1998-03-01), Kamperman et al.
patent: 5777379 (1998-07-01), Karavakis et al.
patent: 5821608 (1998-10-01), DiStefano et al.
patent: 5861666 (1999-01-01), Bellaar
patent: 5895970 (1999-04-01), Miyoshi
patent: 5971253 (1999-10-01), Gilleo et al.
patent: 6022759 (2000-02-01), Seki et al.
patent: 6048753 (2000-04-01), Farnworth et al.
patent: 616
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Nelms David
Vu David
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