Apparatus and method of wordline/bitline redundancy control...

Details Apparatus and method of wordline/bitline redundancy control... Apparatus and method of wordline/bitline redundancy control...

2005-04-26

2005-04-26

Lam, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S189120, C365S230060

Reexamination Certificate

active

06885596

ABSTRACT:
A decoder for use in wordline/bitline redundancy control is disclosed. In one aspect, the decoder includes first and second wordlines respectively coupled to redundant first and second wordlines, where the first and second wordlines are configured to be activated based on decoded first and second addresses. In addition, the decoder includes first and second shift registers respectively coupled to the redundant first and second wordlines, where each is configured to respectively activate the redundant first and second wordlines when the first or second wordlines contain a defect. In addition, a method of selecting wordlines for use in wordline/bitline redundancy control and a wordline decoder having redundancy control capabilities are also disclosed.

REFERENCES:
patent: 6363020 (2002-03-01), Shubat et al.

Affiliated with

Also associated with

Rating

Apparatus and method of wordline/bitline redundancy control... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Apparatus and method of wordline/bitline redundancy control..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method of wordline/bitline redundancy control... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3370850