Apparatus and method for verifying target circuit

Details Apparatus and method for verifying target circuit Apparatus and method for verifying target circuit

2011-04-19

2011-04-19

Trimmings, John P (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S037000, C714S039000, C714S707000, C714S724000, C714S732000, C714S735000, C714S736000, C714S741000, C714S744000, C703S001000, C703S002000, C703S003000, C703S004000, C703S013000, C703S014000, C703S015000, C703S016000, C703S017000, C703S019000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07930609

ABSTRACT:
A circuit verifying method is provided for a logic circuit of a first sequential circuit which outputs a first data based on an input data in synchronization with a first clock signal, and a second sequential circuit which outputs a second data based on the first data in synchronization with a second clock signal with a period longer than that of a first clock signal. The circuit verifying method includes detecting a change of the input data in synchronization with the first clock signal; outputting a data indicating a meta stable state during a period longer than one period of the first clock signal based on the change of the input data as the first data; storing the changed input data in a storage unit based on the change of the input data; and outputting the changed input data which has been stored in the storage unit as the first data after stop the output of the data indicating the meta stable state.

REFERENCES:
patent: 6353906 (2002-03-01), Smith et al.
patent: 6359479 (2002-03-01), Oprescu
patent: 6567961 (2003-05-01), Jacob
patent: 7289946 (2007-10-01), Lee
patent: 7698118 (2010-04-01), Reblewski
patent: 2002/0073383 (2002-06-01), Jacob
patent: 2005/0216247 (2005-09-01), Ikeda et al.
patent: 2005/0229127 (2005-10-01), Warren
patent: 2005/0268265 (2005-12-01), Ly et al.
patent: 2006/0090149 (2006-04-01), Blanco et al.
patent: 2006/0190858 (2006-08-01), Chu et al.
patent: 2008/0040695 (2008-02-01), Chu et al.
patent: 2008/0134115 (2008-06-01), Ly et al.
patent: 2001-229211 (2001-08-01), None

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