Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-08-15
2006-08-15
Chung, Phung My (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S752000
Reexamination Certificate
active
07093181
ABSTRACT:
Disclosed is an apparatus for generating an error detection information bit sequence for determining a length of data sequence transmitted in a communication system. The apparatus comprises a plurality of cascaded registers, the number of which is identical to the number of bits in the error detection information bit sequence, and a plurality of adders arranged on paths determined by a predetermined generator polynomial, each of the adders adding a bit sequence received through an input path to a feedback bit sequence. During reception of the control information sequence, an operator generates the feedback bit sequence by sequentially adding bits of the control information sequence to output bits of a final register and provides the generated feedback bit sequence to the adders. After completion of receiving the control information sequence, the operator sequentially adds a preset input bit to output bits of the final register and outputs the addition result as the error detection information bit sequence. An initial value controller provides the registers with a selected one of two initial values separately determined for the two data sequences.
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Choi Ho-Kyu
Kim Dong-Hee
Kim Youn-Sun
Kwon Hwan-Joon
Chung Phung My
Dilworth & Barrese LLP
Samsung Electronics Co,. Ltd.
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