Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2001-07-26
2004-01-13
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S189080, C365S193000, C365S194000, C365S233100
Reexamination Certificate
active
06678193
ABSTRACT:
This application claims priority from Korean Priority Document No. 00-43323, filed on Jul. 21, 2000 with the Korean Industrial Property Office, which document is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus and method for using echo clocks. More particularly the invention relates to synchronous memory products and related methods for outputting data according to echo clocks without permitting skew to develop, while adapting to changes in the operating cycle due to high speed operations and the like.
2. Brief Description of the Prior Art
Most synchronous products tend to require echo clocks. For instance, in semiconductor memory devices, echo clocks are synchronous signals generated with internal data outputs, and serve as strobe signals to be provided to peripheral systems for tracking the data outputs. The echo clocks are thus also called strobe clocks. In other words, echo clocks are generated by the request of a chip utilizing system.
In the case of semiconductor memory chips, the system uses the echo clock (also referred to as “CQ”) as a reference clock for inputting output data (Dout), which are also referred to as “DQ”. Accordingly, DQ should be provided to a system under the identical condition as CQ at all times, without allowing any skew to develop. As a result, it is possible to maximize setup and hold margin time of the DQ. The aforementioned factor influences the stabilization and speedup of the system.
Speed skews have generally appeared between data and echo clocks due to changes in the operating cycles of the chip. The frequency of operating cycles is reduced, as the chip speeds up. The reduction of the frequency of the operating cycles results in an increase of data outputting speed. However, the echo clocks have been generated at a constant speed regardless of the frequency of the operating cycles, which results in speed skews between outputting data and echo clocks.
The situation is even more of a problem in ultra-high speed semiconductor memory devices using echo clocks, for instance, in synchronous double data rate static products. Skew is even more certain to be generated, which causes operational instability of the system, and failure in speedup of the system.
It is desired to have a semiconductor memory device that presents no skew at either long cycles or short cycles, does not present needless delays, is not complex, and may still perform read and write operations.
SUMMARY OF THE INVENTION
It is an object of the present invention to solve the aforementioned problems.
Accordingly, the invention provides an output buffer that has a data unit for buffering data for an off chip driver. The output buffer also includes an echo clock signal generator for generating an echo clock signal associated with the buffered data. The echo clock signal is generated responsive to either a buffer control signal that controls the data unit, or to the data itself.
A method includes buffering data for an off chip driver, and generating and outputting to the off chip driver an echo clock signal to accompany the data. The echo clock signal is generated responsive to either a buffer control signal that controls the data unit or to the data itself.
The present invention therefore provides semiconductor memory devices that present no skew at either long cycles or short cycles, do not present needless delays, are not complex, and may still perform read and write operations.
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Harold Pilo, et al. (IBM Microelectronics, Essex Junction, VT); ISSCC 2000 / Session 16 / Non-Volatile and SRAM / Paper TP 16.2; “Variable Delay Clock Driver and Data-to-Echo Tracking System”; IEEE, ISSCC 2000 Slide Supplement; pp. 214, 215.
Kim Young-Tae
Park Chul-Sung
Lebentritt Michael S.
Luu Pho
Marger & Johnson & McCollom, P.C.
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