Apparatus and method for thermal isolation, circuit cooling...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S411000, C438S422000, C257S709000

Reexamination Certificate

active

07033927

ABSTRACT:
The disclosure relates to method and apparatus for isolating sensitive regions of a semiconductor device by providing a thermal path or an electromagnetic shield. The thermal path may include vias having different length, depth and configuration such that the thermal path between the two regions is lengthened. In addition, the vias may be fully or partially filled with an insulating material having defined conductive properties to further retard heat electromagnetic or heat transmission between the regions. In another embodiment, electrical isolation between two regions is achieved by etching a closed loop or an open loop trench at the border of the regions and filling the trench with a conductive material to provide proper termination of electromagnetic fields within the substrate.

REFERENCES:
patent: 6100199 (2000-08-01), Joshi et al.
patent: 2002/0033189 (2002-03-01), Macris
Wu, J.H., et al., “A Faraday Cage Isolation Structure for Substrate Crosstalk Suppression,” IEEE Microwave and Wireless Components Letters, vol. 11, No. 10, Oct. 2001.
Soh, H.T., et al., “Ultra-Low Resistance, Through-Wafer VIA (TWV) Technology and its Applications in Three Dimensional Structures on Silicon,” Japanese Journal of Applied Physics, vol. 38, 1999.
Wu, j., et al., “A High Aspect Ratio Silicon Substrate-Via Technnology and Applications: Through-Wafer Interconnects for Power and Ground and Faraday Cages for SOC Isolation,” IEDM, 2000.

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