Apparatus and method for testing and debugging an integrated...

Details Apparatus and method for testing and debugging an integrated... Apparatus and method for testing and debugging an integrated...

2009-07-09

2011-12-06

Trimmings, John (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S734000, C714S028000, C714S030000, C714S724000, C714S733000, C714S741000, C714S726000, C714S727000, C703S028000, C703S023000, C711S001000, C370S366000

Reexamination Certificate

active

08074135

ABSTRACT:
An integrated circuit includes an embedded processor. An embedded in-circuit emulator is located within the embedded processor. The embedded in-circuit emulator performs a test on the integrated circuit. The embedded in-circuit emulator generates a testing result based on the test on the integrated circuit. Trace logic to generate trace data based on the testing result, the trace data being in a parallel format. A serializer is located on the integrated circuit. The serializer converts the parallel format of the trace data into a serial format. The serializer serially outputs the trace data in the serial format from the integrated circuit.

REFERENCES:
patent: 4674089 (1987-06-01), Poret et al.
patent: 4897837 (1990-01-01), Ishihara et al.
patent: 5649129 (1997-07-01), Kowert
patent: 5689515 (1997-11-01), Panis
patent: 5764952 (1998-06-01), Hill
patent: 5771240 (1998-06-01), Tobin et al.
patent: 5781560 (1998-07-01), Kawano et al.
patent: 5812562 (1998-09-01), Baeg
patent: 5978870 (1999-11-01), Warren
patent: 5978937 (1999-11-01), Miyamori et al.
patent: 6028983 (2000-02-01), Jaber
patent: 6115763 (2000-09-01), Douskey et al.
patent: 6125416 (2000-09-01), Warren
patent: 6148381 (2000-11-01), Jotwani
patent: 6167365 (2000-12-01), Karthikeyan et al.
patent: 6189115 (2001-02-01), Whetsel
patent: 6279051 (2001-08-01), Gates et al.
patent: 6282674 (2001-08-01), Patel et al.
patent: 6289300 (2001-09-01), Brannick et al.
patent: 6314530 (2001-11-01), Mann
patent: 6321354 (2001-11-01), Prunier
patent: 6356960 (2002-03-01), Jones et al.
patent: 6389558 (2002-05-01), Herrmann et al.
patent: 6401191 (2002-06-01), Jones
patent: 6421795 (2002-07-01), Yamashita
patent: 6457124 (2002-09-01), Edwards et al.
patent: 6459393 (2002-10-01), Nordman
patent: 6523136 (2003-02-01), Higashida
patent: 6526501 (2003-02-01), Edwards et al.
patent: 6642736 (2003-11-01), Mori et al.
patent: 6665737 (2003-12-01), Edwards
patent: 6687857 (2004-02-01), Iwata et al.
patent: 6690189 (2004-02-01), Mori et al.
patent: 6779133 (2004-08-01), Whetsel
patent: 6813732 (2004-11-01), Kurooka et al.
patent: 6820051 (2004-11-01), Swoboda
patent: 6834367 (2004-12-01), Bonneau et al.
patent: 6865222 (2005-03-01), Payne
patent: 6868376 (2005-03-01), Swoboda
patent: 6918058 (2005-07-01), Miura et al.
patent: 6957180 (2005-10-01), Nemecek
patent: 6973592 (2005-12-01), Debling
patent: 7003599 (2006-02-01), Warren et al.
patent: 7007201 (2006-02-01), Byrne et al.
patent: 7010612 (2006-03-01), Si et al.
patent: 7031903 (2006-04-01), Debling
patent: 7076708 (2006-07-01), Faust et al.
patent: 7080789 (2006-07-01), Leaming
patent: 7096310 (2006-08-01), Norden
patent: 7127649 (2006-10-01), Learning
patent: 7197680 (2007-03-01), Kimelman et al.
patent: 7216276 (2007-05-01), Azimi et al.
patent: 7278073 (2007-10-01), Kimelman et al.
patent: 7327725 (2008-02-01), Schriel et al.
patent: 7350121 (2008-03-01), Creigh
patent: 7363564 (2008-04-01), Moss et al.
patent: 7412633 (2008-08-01), Kimelman et al.
patent: 7444546 (2008-10-01), Kimelman et al.
patent: 7444571 (2008-10-01), Azimi et al.
patent: 7496812 (2009-02-01), Azimi et al.
patent: 7496818 (2009-02-01), Azimi et al.
patent: 2002/0026553 (2002-02-01), Saito
patent: 2002/0184001 (2002-12-01), Yao
patent: 2004/0078690 (2004-04-01), Kohashi
patent: 2004/0221201 (2004-11-01), Seroff
IEEE Standard 1149.1-2001 (Revision of IEEE Std 1149.1-1990), IEEE Standard Test Access Port and Boundary-Scan Architecture, (208 pp.).
IEEE Standard Standard Test Access Port and Boundary-Scan Architecture, Institute of Electrical and Electronics Engineers (IEEE) as IEEE Standard 1149.1-2001, pp. 1-200.

Affiliated with

Also associated with

Rating

Apparatus and method for testing and debugging an integrated... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Apparatus and method for testing and debugging an integrated..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for testing and debugging an integrated... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4294807