Apparatus and method for testing and debugging an integrated...

Details Apparatus and method for testing and debugging an integrated... Apparatus and method for testing and debugging an integrated...

2005-07-11

2009-02-24

Trimmings, John P (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S030000, C714S045000, C714S724000, C714S734000, C714S741000, C703S028000, C341S100000, C375S224000, C370S366000

Reexamination Certificate

active

07496818

ABSTRACT:
A system is provided that retrieves test information from a target integrated circuit. A serializer receives the test information in a first format and divides and reformats the test information into first and second serial messages. The serializer is located on the target integrated circuit and has a first serial output that sends the first serial message and a second serial output that sends the second serial message. A deserializer communicates with the first and second serial outputs and receives the first and second serial messages. The deserializer retrieves a first portion of the test information from the first serial message, a second portion of the test information from the second serial message, and reconstructs the test information from the first portion and the second portion.

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IEEE Standard 1149.1, IEEE Standard Test Access Port and Boundary-Scan Architecture, 2001, 208 pages.

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