Apparatus and method for testing and debugging an integrated...

Details Apparatus and method for testing and debugging an integrated... Apparatus and method for testing and debugging an integrated...

2005-02-24

2008-10-28

Trimmings, John P (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S724000, C714S734000, C714S030000, C714S045000, C703S028000

Reexamination Certificate

active

07444571

ABSTRACT:
A system for testing a target integrated circuit comprises a host device that executes a debugging and testing analysis program, that transmits test instructions and data to the integrated circuit and that analyzes received data from the target integrated circuit. A first interface module communicates with the host device and formats the test instructions and data using a first format. A first serializer serializes the test instructions and data. A first deserializer on the target integrated circuit communicates with the first serializer and deserializes the test instructions and data. A control module on the target integrated circuit communicates with the first deserializer, interprets the test instructions and data using the first format. A testing module receives the interpreted test instructions and data from the control module and performs testing and debugging of the target integrated circuit.

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IEEE Standard 1149.1, IEEE Standard Test Access Port and Boundary-Scan Architecture, 2001, 208 pages.

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