Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2007-04-17
2007-04-17
Nguyen, Van Thu (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S200000, C365S230080, C714S718000, C714S730000
Reexamination Certificate
active
11118223
ABSTRACT:
An apparatus includes a test signal path to provide a test signal to a memory cell array responsive to an address generating command, the test signal to access a memory cell within the memory cell array, a failure address path to generate a failure address responsive to the address generating command, and a failure discriminator to determine a result responsive to the access, the result to indicate whether the memory cell is faulty, and to store the result according to the failure address.
REFERENCES:
patent: 5588115 (1996-12-01), Augarten
patent: 6504773 (2003-01-01), Kobayashi
patent: 6523143 (2003-02-01), Kobayashi
patent: 2004/0145933 (2004-07-01), Yamane
patent: 5-80125 (1993-04-01), None
patent: 08-146098 (1996-06-01), None
patent: 1996-0019322 (1996-06-01), None
patent: 1998-024686 (1998-07-01), None
English language abstract of Korean Publication No. 1998-024686.
English language abstract of Korean Publication No. 1996-0019322.
English language abstract of Japanese Publication No. 5-80125.
English language abstract of Japanese Publication No. 08-146098.
Marger & Johnson & McCollom, P.C.
Nguyen Van Thu
Samsung Electronics Co,. Ltd.
LandOfFree
Apparatus and method for testing a memory device with... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and method for testing a memory device with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for testing a memory device with... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3764786