Apparatus and method for separately layering cache and architect

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

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711118, G06F 1300

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active

059095610

ABSTRACT:
Cache and architectural functions within a cache controller are layered and provided with generic interfaces, isolating controller logic from specific architectural complexities. Controller logic may thus be readily duplicated to extend a nonshared cache controller design to a shared cache controller design, with only straightforward modifications required. Throttling of processor-initiated operations handled by the same controller logic resolves operation flow rate issues with acceptable performance trade-offs.

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