Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-04-14
1999-06-01
Sheikh, Ayaz R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711118, G06F 1300
Patent
active
059095610
ABSTRACT:
Cache and architectural functions within a cache controller are layered and provided with generic interfaces, isolating controller logic from specific architectural complexities. Controller logic may thus be readily duplicated to extend a nonshared cache controller design to a shared cache controller design, with only straightforward modifications required. Throttling of processor-initiated operations handled by the same controller logic resolves operation flow rate issues with acceptable performance trade-offs.
REFERENCES:
patent: 4901230 (1990-02-01), Chen et al.
patent: 4926363 (1990-05-01), Nix
patent: 5175829 (1992-12-01), Stumpf et al.
patent: 5235688 (1993-08-01), Taniguchi et al.
patent: 5276852 (1994-01-01), Callander et al.
patent: 5276902 (1994-01-01), Nakatani et al.
patent: 5408627 (1995-04-01), Stirk et al.
patent: 5544345 (1996-08-01), Carpenter et al.
patent: 5553263 (1996-09-01), Kalish et al.
patent: 5598550 (1997-01-01), Shen et al.
patent: 5644753 (1997-07-01), Ebrahim et al.
patent: 5710905 (1998-01-01), Wan
patent: 5732408 (1998-03-01), Takahashi
patent: 5748985 (1998-05-01), Kanai
patent: 5751983 (1998-05-01), Abramson et al.
Arimilli Ravi Kumar
Dodson John Steven
Lewis Jerry Don
Williams Derek Edward
Dillon Andrew J.
Henkler Richard A.
International Business Machines - Corporation
Sheikh Ayaz R.
Thai Xuan M.
LandOfFree
Apparatus and method for separately layering cache and architect does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and method for separately layering cache and architect, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for separately layering cache and architect will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-961285