Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Reexamination Certificate
2007-05-15
2007-05-15
Elmore, Stephen C. (Department: 2185)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
C711S001000, C711S100000, C711S118000, C711S127000, C711S131000, C711S149000, C365S230030, C365S230040, C365S230050, C712S205000, C712S206000
Reexamination Certificate
active
10829621
ABSTRACT:
A processor having the capability to dispatch multiple parallel operations, including multiple load operations, accesses a cache which is divided into banks. Each bank supports a limited number of simultaneous read and write access operations. A bank prediction field is associated with each memory access operation. Memory access operations are selected for dispatch so that they are predicted to be non-conflicting. Preferably, the processor automatically maintains a bank predict value based on previous bank accesses, and a confirmation value indicating a degree of confidence in the bank prediction. The confirmation value is preferably an up-or-down counter which is incremented with each correct prediction and decremented with each incorrect prediction.
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Elmore Stephen C.
Kim Daniel
Truelson Roy W.
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