Apparatus and method for recalibrating a source-synchronous...

Details Apparatus and method for recalibrating a source-synchronous... Apparatus and method for recalibrating a source-synchronous...

2005-07-26

2005-07-26

Browne, Lynne H. (Department: 2116)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C710S104000

Reexamination Certificate

active

06922789

ABSTRACT:
An SMP computer system has an apparatus and method for recalibrating a self-timed, source-synchronous, pipelined interface while the computer system is running. The apparatus allows for quiescing the interface (ie. idling the processors to allow for no data transfers), raising fences (blocking interfaces), allowing for a quick clock centering recalibration step, and then unfencing and unquiescing to allow for the use of the interface again. The recalibration allows for compensating for drift over time on the interface to compensate for temperature, voltage, cycle time, and end-of-life degradation without bringing down and restarting the system.

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