Apparatus and method for random pattern built in self-test

Details Apparatus and method for random pattern built in self-test Apparatus and method for random pattern built in self-test

2007-08-14

2007-08-14

Decady, Albert (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

10021374

ABSTRACT:
An apparatus permits built-in self-test (“BIST”) of an IC that includes a memory element having more than one impermissible operation. A code generator accepts a clock signal and generates a test code in response to it. A decoder accepts the test code and generates at least two output lines to disable the impermissible operations during the test. When the decoder is in a decode disabled condition, the output lines reflect a value that permit all possible memory operations.

REFERENCES:
patent: 5974579 (1999-10-01), Lepejian et al.
patent: 6014336 (2000-01-01), Powell et al.
patent: 6463422 (2002-10-01), Hangartner
“Logic Design Principles With Emphasis On Testable Semicustom Circuits” by Edward J. McCluskey, published by Prentice-Hall. 1986. Section 10.6 pp. 455-474.

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