Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2000-12-29
2002-10-22
Le, Vu A. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S149000
Reexamination Certificate
active
06469941
ABSTRACT:
TECHNICAL FIELD
The present invention relates to memory and, in particular, to an apparatus and method for pumping memory cells in a memory.
BACKGROUND
In dynamic random access memories (DRAM), densities are increasing and operating voltages are decreasing. In addition, DRAMs are now being embedded with other logic and functionality on a single integrated circuit (IC). The technological drive toward higher densities, lower operating voltages and embeddedness for DRAMs are all contributing to a decreasing differential signal voltage (related to noise margin) detected on the bit lines during the read operation of a memory cell.
Accordingly, there exists a need for a method and apparatus for increasing the differential signal voltage detected during a read operation on the bit lines of a memory without the need for additional complex circuitry.
SUMMARY OF THE INVENTION
According to the present invention, there is provided a memory having a first bit line and a charge-storing element having a first plate and a second plate, with an access device having a first end coupled to the first bit line, a second end coupled to the first plate of the charge-storing element thereby defining a node, and a control terminal coupled to a word line. A voltage driver circuit coupled to the second plate of the charge-storing element provides, a high logic level voltage to the second plate of the charge-storing element when a low logic level is present on a second bit line, a low logic level voltage to the second plate of the charge-storing element when a high logic level voltage is present on the second bit line, and substantially the same voltage as an intermediate voltage to the second plate of the charge-storing element when the intermediate voltage level is present on the second bit line. The second bit line may be the same as the first bit line (true) or a complement bit line.
In another embodiment of the present invention, there is provided a memory having a first bit line, a charge-storing element having a first plate and a second plate, and an access device having a first end, a second end and a control terminal, the first end coupled to the first bit line, the second end coupled to the first plate of the charge-storing element and defining a node, the control terminal coupled to a word line, with the access device for coupling and decoupling the node from the first bit line. A voltage driver circuit coupled to the second plate of the charge-storing element applies a first voltage to the second plate of the charge-storing element when the access device is activated and a second voltage is applied to the node, and applies a third voltage to the second plate after the access device is deactivated.
In yet another embodiment of the present invention, there is provided a method of pumping a memory. A word line is activated for coupling a first plate of a memory cell to a first bit line. A sense amplifier coupled to the first bit line and a second bit line is activated for detecting a voltage differential between the first bit line and the second bit line. A high logic voltage value is applied to the first bit line and a low logic voltage value is applied to the second bit line. A first voltage is applied to a second plate of the memory cell. The word line is deactivated for decoupling the first plate of the memory cell from the first bit line. After the word line is deactivated, a second voltage greater than the first voltage is applied to the second plate of the memory.
In still another embodiment of the present invention, there is provided a method of pumping a memory. A first bit line and a second bit line are precharged and equilibrated to an intermediate voltage, the intermediate voltage having a magnitude between a first voltage and a second voltage representing a logic high and a logic low, respectively. A word line is activated for coupling a first plate of a memory cell to a first bit line. A sense amplifier coupled to the first bit line and a second bit line is activated. The first voltage is applied to the first bit line and the second voltage is applied to the second bit line. The second voltage is applied to a second plate of the memory cell. The word line is deactivated for decoupling the first plate of the memory cell from the first bit line. After the word line is deactivated, a third voltage is applied to the second plate of the memory wherein the third voltage is substantially equal to the intermediate voltage.
REFERENCES:
patent: 4769784 (1988-09-01), Doluca et al.
patent: 5255232 (1993-10-01), Foss et al.
patent: 5414656 (1995-05-01), Kenney
patent: 5508962 (1996-04-01), McLaughlin et al.
patent: 5734603 (1998-03-01), Tai
patent: 6081459 (2000-06-01), Kim
patent: 6236598 (2001-05-01), Chou
Asakura et al., “Cell-Plate Line Connecting Complementary Bit-Line (C3) Architecture for Batter-Operating DRAM'S”, IEEE Journal of Solid-State Circuits, Apr. 1992, pp. 597-602, V. 27, No. 4.
Fujishima et al., “A Storage-Node-Boosted RAM with Word-Line Delay Compensation”, IEEE Journal of Solid-State Circuits, Oct. 1982, pp. 872-876, V. SC-17, No. 5.
Jorgenson Lisa K.
Le Vu A.
Phung Anh
STMicroelectronics Inc.
LandOfFree
Apparatus and method for pumping memory cells in a memory does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and method for pumping memory cells in a memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for pumping memory cells in a memory will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2920619